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AM5728: Build shared library in OREO

March 6, 2019, 12:16 am
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LM5036: 280W Isolated DC-DC converter

March 6, 2019, 12:24 am
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Part Number:LM5036

Hi !

I am  building a GaN FET based half-bridge converter with the controller LM5036. The parameters are:

1. Input Voltage: Vin=36-75V  DC

2. Output Voltage: Vout=28V

3. Output Current : Iout=10A.

4. Frequency: fsw=1 MHz

I have a few questions:

1.  The VCC of LM5036 is from 8V to 16V, so its outputs (HSG/LSG)  can not directly drive GaN FET .Designed to drive GaN FET using LMG1205, HSG and LSG are connected to LMG1205's HI and LI respectively.     Is that appropriate?

2.  The fsw is 1MHz and oscillator frequency is 2 MHz, is there a special requirement for opto-coupler between primary and second?  Can I use the PS2811-1 which is used in lm5036EVM-294? If not, do you have some to recommend?

Lin

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TAS5805M: Evaluation of TAS5808M

March 6, 2019, 12:26 am
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Part Number:TAS5805M

My customer is evaluating TAS5808M for monitor applications.

They would like to confirm the below specification which can be done by TAS5808M or need extra external components for it? Thank for your help.

 

Built-in Dynamic Range Control (DRC) or automatic gain control (AGC)

Required to limit the amplifier output THD < 1%

(ref target, to confirm specs at P1)

Built-in Adjustable EQ (no of bands)

5 bnads factory programmable. Not accessible by user.

Amp Output Power (Avg at THD 1%)

2 X 1W

Internal Speaker Amp Output
(Electrical Measurement: Into System speaker load; i.e. 4 ohm, 8 ohm etc. System set to Max Volume)

　

　

　

　

　

THD+N [ Acoustic Speaker Performance] At rated amplifier power

<= -26 db (5%)

Line output crosstalk [across FR of Acoustic Speaker Performance]

>=30 dB

Pop and Click performance

<-60dBV

Amplifier Power Rating (minimum)

1.0x the rated speaker power

Amplifier Gain Options

12dB and 16dB; Other gain options can be considered

 Thank for your help.

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TAS5411-Q1: SCL/SDA-pin status in Standby mode

March 6, 2019, 12:26 am
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Part Number:TAS5411-Q1

Hi Experts,

I want to know whether SDA/SCL terminals are Hi-impedance while in standby mode. I beliave it is Hi-impedance. Is my understanding correct? Also I want to know why capacitance value is SDA terminal is changed between Play mode and Standby mode. Why?

Best Regards,
Fujiwara

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CDCLVP1208: Vout_diff using LVPECL

March 6, 2019, 12:28 am
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Part Number:CDCLVP1208

Dear Team,

My customer wants to use the CDCLVP1208 for their clock distribution.

On the datasheet :

On first page :

Will it be safe to assume we can get VOut_diff of 1.15Vpp at 250MHz ?

Regards,

Nir.

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DS90CR288A: Receiver Switching Characteristics

March 6, 2019, 12:29 am
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Part Number:DS90CR288A

Hi, team,

Could you please Receiver Switching Characteristics with f=50MHz?
(These characteristics in datasheet are for f=85MHz.)

Regards,
Nagata.

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Linux/AM5749: Processor SDK Open CL license

March 6, 2019, 12:29 am
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Part Number:AM5749

Tool/software: Linux

Hi Champs,

TI processor SDK suppurt Open CL software for Deep learning or video processing.

Could you please tell us who is this license owner ?

Does customer need care this license to release their production ?

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CC3220SF-LAUNCHXL: Question about RF Calibration & Data Rate Change Operation Confirmation & Setting Method.

March 6, 2019, 12:32 am
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Part Number:CC3220SF-LAUNCHXL

Dear Experts.

I have a Question for  RF Calibration & Data Rate Change Operation Confirmation & Setting Method.

1) Is there a way to verify that the RF calibration has been done when I change the TX Level periodically?

    - The current calibration mode is Normal.

2) Is there a way to confirm or change the speed of the data depending on the RF environment?

   - For example, network environment is congested and WiFi automatically keeps bandwidth or transmission speed down to keep it working smoothly. (N->G, 54Mbps -> 11Mbps)

   - Does the CC3220SF have an API that can change the mode or change the speed arbitrarily depending on the environment?

   - Or if there is a change in mode or baud rate automatically depending on the network environment, is there a way to check the setting value of the change?

   - If it is possible, I would appreciate notifying you of the conditions and the API.

 

Thank you

Br IK

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ADS7953: CS PIN SWITCHING

March 6, 2019, 12:32 am
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Part Number:ADS7953

HI,

from datasheet i checked that CS pin has to be switch for each frame in any mode to get data, but what will happen if i make CS pin low for first time and then keep it low and continuously provide clock pulses to read all 16 channels ? (16*16 clock pulses). will i get all channel value or will get dummy data ?

Regard,

Nilesh koladiya

7045119667

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RTOS/IWR1443BOOST: IWR1443BOOST

March 6, 2019, 12:33 am
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Part Number:IWR1443BOOST

Tool/software: TI-RTOS

How can I know the distance between the antenna? And how to get the angle according to the range-doppler fft(2D-FFT)?I learnt from the video that we 

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CCS/TM4C1294NCPDT: Not able to observe uart transferred data by using udma in com port

March 6, 2019, 12:34 am
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Part Number:TM4C1294NCPDT

Tool/software: Code Composer Studio


Hii,

I'am transferring data from memory to uart by using udma controller.If i'am enabling the loop back by using (HWREG(UART1_BASE + UART_O_CTL) |= UART_CTL_LBE) then we are able to see the data in ui8RxBufA,ui8RxBufB buffers but we are not able to get the transferred data in uart com port.


#define MEM_BUFFER_SIZE 1024

#define UART_TXBUF_SIZE 256

#define UART_RXBUF_SIZE 256

static uint8_t g_ui8TxBuf[UART_TXBUF_SIZE];

static uint8_t g_ui8RxBufA[UART_RXBUF_SIZE];

static uint8_t g_ui8RxBufB[UART_RXBUF_SIZE];

static uint32_t g_ui32RxBufACount = 0;

static uint32_t g_ui32RxBufBCount = 0;

void UART1IntHandler(void)

{

uint32_t ui32Status;

uint32_t ui32Mode;

 ui32Status = UARTIntStatus(UART1_BASE, 1);

UARTIntClear(UART1_BASE, ui32Status);


 ui32Mode = uDMAChannelModeGet(UDMA_CHANNEL_UART1RX | UDMA_PRI_SELECT);

if(ui32Mode == UDMA_MODE_STOP)

{

g_ui32RxBufACount++;

uDMAChannelTransferSet(UDMA_CHANNEL_UART1RX | UDMA_PRI_SELECT,UDMA_MODE_PINGPONG,(void *)(UART1_BASE + UART_O_DR),g_ui8RxBufA, sizeof(g_ui8RxBufA));

}

 ui32Mode = uDMAChannelModeGet(UDMA_CHANNEL_UART1RX | UDMA_ALT_SELECT);

if(ui32Mode == UDMA_MODE_STOP)

{

g_ui32RxBufBCount++;

uDMAChannelTransferSet(UDMA_CHANNEL_UART1RX | UDMA_ALT_SELECT,UDMA_MODE_PINGPONG,(void *)(UART1_BASE + UART_O_DR),g_ui8RxBufB, sizeof(g_ui8RxBufB));

}

if(!uDMAChannelIsEnabled(UDMA_CHANNEL_UART1TX))

{

uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT,UDMA_MODE_BASIC, g_ui8TxBuf,(void *)(UART1_BASE + UART_O_DR),sizeof(g_ui8TxBuf));

uDMAChannelEnable(UDMA_CHANNEL_UART1TX);

}

}

void InitUART1Transfer(void)

{

uint_fast16_t ui16Idx;

for(ui16Idx = 0; ui16Idx < UART_TXBUF_SIZE; ui16Idx++)

 g_ui8TxBuf[ui16Idx] = 'A';

SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);

SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART1);


UARTConfigSetExpClk(UART1_BASE, ui32SysClkFreq, 115200,UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |UART_CONFIG_PAR_NONE);

UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);


UARTEnable(UART1_BASE);

UARTDMAEnable(UART1_BASE, UART_DMA_RX | UART_DMA_TX);

HWREG(UART1_BASE + UART_O_CTL) |= UART_CTL_LBE;

IntEnable(INT_UART1);

///////receiving parameter

uDMAChannelAttributeDisable(UDMA_CHANNEL_UART1RX,UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK);

uDMAChannelControlSet(UDMA_CHANNEL_UART1RX | UDMA_PRI_SELECT,UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4);

uDMAChannelControlSet(UDMA_CHANNEL_UART1RX | UDMA_ALT_SELECT,UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4);

uDMAChannelTransferSet(UDMA_CHANNEL_UART1RX | UDMA_PRI_SELECT,UDMA_MODE_PINGPONG,(void *)(UART1_BASE + UART_O_DR),g_ui8RxBufA, sizeof(g_ui8RxBufA));

uDMAChannelTransferSet(UDMA_CHANNEL_UART1RX | UDMA_ALT_SELECT,UDMA_MODE_PINGPONG,(void *)(UART1_BASE + UART_O_DR),g_ui8RxBufB, sizeof(g_ui8RxBufB));


/////////transimitting paramter

uDMAChannelAttributeDisable(UDMA_CHANNEL_UART1TX,UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK);

uDMAChannelAttributeEnable(UDMA_CHANNEL_UART1TX, UDMA_ATTR_USEBURST);

uDMAChannelControlSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT,UDMA_SIZE_8 | UDMA_SRC_INC_8 |UDMA_DST_INC_NONE | UDMA_ARB_4);

uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT,UDMA_MODE_BASIC, g_ui8TxBuf,(void *)(UART1_BASE + UART_O_DR),sizeof(g_ui8TxBuf));


uDMAChannelEnable(UDMA_CHANNEL_UART1RX);

uDMAChannelEnable(UDMA_CHANNEL_UART1TX);


UARTIntEnable(UART1_BASE, UART_INT_DMATX | UART_INT_DMATX);

}

int main(void)

{

 ui32SysClkFreq = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 120000000);

SysCtlPeripheralClockGating(true);

SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);

SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);

IntEnable(INT_UDMAERR);

uDMAEnable();

uDMAControlBaseSet(pui8ControlTable);

InitUART1Transfer();

}

Thanks and Best Regards,

Anamika

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AM4376: DDR_VREF power-up sequence

March 6, 2019, 12:41 am
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Part Number:AM4376

Hi everyone,

Please let me know about the power up sequence of DDR_VREF.

On my customer's board, DDR_VREF rise after 4msec of VDDS_DDR.
Is this sequence correct?

There is no DDR_VREF in the following sequence diagram of DS.

My customer should start DDR_VREF at this timing in this sequence?

Best regards,
Sasaki

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THS4551: 8th active filter quality factor calculation

March 6, 2019, 12:44 am
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Part Number:THS4551

Hello, 

I have a differential 8th order active filter (It includes 4 x 2nd order active filters) and four quality factor. (Q1,Q2,Q3,Q4).

How can I find or calculate totally quality factor of 8th order active filter? 

Thanks.

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UCC24624: LLC topologie up to 3KW and behaviour during burst mode and short circuit

March 6, 2019, 12:44 am
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Part Number:UCC24624

Hi,

do someone have used the UCC24624 duak channel synchronous rectifier in LLC topologie up to 3KW output power : 48V 45A.

The primary side is a UCC256302 controller.

My questions are  about the beaviour of the UCC24624 in Burst mode with no load and restart after short circuit .

Do the UCC24624 is still used and tested with this power and under all these electrics stress?

Thank you per advance.

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LMG5200: Class D Amp

March 6, 2019, 12:50 am
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Part Number:LMG5200

Hi Team,

do we have any collateral related to building a Class D Amp that can switch at around 10Mhz? Maybe based on the LMG5200 or the LMG1210?

Regards,

Mihir

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LMG1205: Issues with transient over-voltage peaks from HS to VSS (

March 6, 2019, 12:59 am
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Part Number:LMG1205

We have been using LMG1205YFXR in our servo drive (inverter) and experiencing some trouble when driving EPC GaN FETs. Our product is intended to work under 80 Vdc nominal, but some high-side transistors have burned as current gets high and working at 80 Vdc. 
We checked Vds and Vgs voltages with a 5 GS/s, 500 MHz BW oscilloscope with super short, calibrated, high bandwidth probes and observed some interesting behaviour under the 10 ns time scale. Please check the following capture:
41_40A_80V_HSoff_D_LSon_Iout.png
As it can be seen, a notable overshoot in the high-side voltage happens during the turn-off of the high-side while current exits the drive. We have observed this voltage as high as 100 V (barely inside the maximum absolute ratings of LMG1205) but only during < 5 ns, and the gate drivers have been working reliably. 
The transistors we are using are well rated at 120 V, well dissipated, with the best possible practices of layout and we are very confident they should not fail. 
However, we would like to know your thoughts about the effects of this extremely short pulses applied to your gate driver. Could they cause an unwanted turn-off (And shoot-through) of the half bridge? May this be an issue with the bootsrap circuit?
Additionally, a notable negative Vgs voltage can be observed during the turn-off of the low-side. Having that the turn-off gate resistor here is a 0 Ω jumper, we are concerned of a negative voltage applied to the "sink" output of the gate driver, but again during an extremely short time. 
44_40A_80V_LSoff_D_HSon_Iin.png
We would like to know your opinion and we are opened to any comments. Do you think any of these could cause failure?
Thanks in advance.
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CC2640R2F: websocket_server.exe in RTLS agent cannot run on 32bit OS

March 6, 2019, 12:59 am
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Part Number:CC2640R2F

Team,


My customer who develops the localization apps using our RTLS - is suffering from a websocket_server.exe 32bit compatibility issue. It seems it built for x86-64 so cannot run on their lap-top.

Is it possible to rebuild/prepare it to be suitable to 32bit OS?

Regards,
Nonaka

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BQ25601D: Charging solution with TPS2121

March 6, 2019, 1:00 am
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Part Number:BQ25601D

Dear Jeff,

Design:

AUX DC 5V 3A

VBUS 5V depends on DFP, the TUSB321 has this info ( 0.5A USB2, 0.9A USB3, 1.5A, 3A)

TPS2121 ILIM -> 3A

as suggested to use BQ25601D and TPS2121 for our application, we looked into the two IC and have some questions:

1) If we have only AUX DC 5V connected to BQ25601D trough TPS2121 and the USB VBUS is not connected.

The charger BQ25601D can't detect what kind of source is connected because there is no D+, D- connection.

What charging current for the battery will the charger set?  

2) Have you a suggestion how the charger can detect that Vin is the AUX DC?

-------------------------------------------------------------------------------------------------------------------------------------------------------

Second topic is we want to realize this states below: ( we think this is typical usage in mobile phone or laptop)

We want to have only one PUSH BUTTON , do we need some button controller to realize this or how is this down with BQ25601D?

Best Regards,

David.

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TMS320F28379D: Comparator subsystem problem

March 6, 2019, 1:01 am
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Part Number:TMS320F28379D

Dear all,

I have trouble with analog comparator module of F29379D. I have set the required registers and applied sin wave to positive pin of comparator. After that, I have connect negative input of the comparator to DAC. However, unfortunately, I could not observe a toggled output.

Here is the settings for comparator module;

        EALLOW;
        Cmpss1Regs.COMPLOCK.all = 0;
        Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;        //comparator/DAC enable
        Cmpss1Regs.COMPCTL.bit.ASYNCHEN = 1;        //High comparator asynchronous path enable
        Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;    //Asynchronous comp output drives CTRIPOUTH signal (to the outputxbar)
        Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 0;     //"             "      "      "    (to the epwm xbar)
        Cmpss1Regs.COMPCTL.bit.COMPHINV = 0;        //non-inverting output of comparator
        Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0;     //negative input is connected to DAC register
        Cmpss1Regs.COMPHYSCTL.bit.COMPHYS = 0;      //no hysteresis
        Cmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 0;    //load DAC value with system clock
        Cmpss1Regs.COMPDACCTL.bit.SELREF = 0;       //DAC reference selection, select VDDA
        Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 0;    //update the DAC from DACVAL register(or ramp generator)
        Cmpss1Regs.DACHVALS.bit.DACVAL = 100;       //the value which is loaded to DAC
        Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 0;    //filter has no effect

        // Configure CTRIPOUTH output pin
        // Configure OUTPUTXBAR3 to be CTRIPOUT1H
        //
        OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 0;
        //
        //Enable OUTPUTXBAR3 Mux for Output
        //
        OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0 = 1;

        EDIS;

and the output pin configuration;

GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 6;    //set GPIO14 pin as OUTPUTXBAR3

I could not understand what is the problem.

I will be waiting for your offer.

Regards;

Fahri

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OPT8241-CDK-EVM: Is there any way to restore 8241EVM to factory Settings?

March 6, 2019, 1:02 am
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Part Number:OPT8241-CDK-EVM

Hello,

My OPT8241-CDK-EVM module(connecting a rpi3 running Linux) was powered off abnormally. At first,  I rebooted the device and  could't run VoxelCLI/Start normally. The built in profiles can't be read normally by the Voxel viewer 0.9.10 running on Windows. Some built in profiles are missing, such as the Extra Long Range profile, but I can read the built-in profiles with VoxelCLI. Then after a while, I rebooted the device again, and VoxelCLI/Start(linux) command can run normally, Voxel viewer 0.9.10 still can't read all the profiles. Is there any way to restore 8241EVM   to factory Settings? 

Flashing OPT9221 E2rom is no use at all. Thanks!

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