Part Number:TMS320F28377S
Good day,
We are working with TMS320F28377S and use a bootloader that writes to bank1 if bank0 was written to earlier and the other way around.
On bank1 we had a curious issue: One of the ADCs just didn't work anymore. While debugging the issue, we noticed that AdcbRegs.ADCINTFLG.bit.ADCINT1 was set and the program would not go into the ISR anymore. At start, the program would go exactly once into the ISR and then ignore the flag.
This ADC is triggered with a PWM at 50kHz and the acquisition time is set to 320ns. As the trigger intervals are 2us, this should not be an issue.
Changing the interrupt to ADCB2 didn't have an effect. Also other ADCs are in use at 1kHz, which are triggered inside a timer ISR, and they work fine on both banks.
When adding this code at the end of the ISR, the ADC started to work again:
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;// Acknowledge interrupt to PIE
if(AdcbRegs.ADCINTFLG.bit.ADCINT1) // didn't work the first time
{
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;// Acknowledge interrupt to PIE
}
Now we have the issue that instead of 50 values each millisecond, we only get 48 to 49, when using bank1. On bank0 it works just fine either way.
This solution is acceptable, but understanding the issue would prevent similar situations in the future and resolving it would ensure that both banks exhibit the same behaviour.
The overall program is rather large, so i can only provide code snippets. I'll try to include all relevant code below.
Thanks,
Daniel
inline void INIT_INTERRUPTS() // called during startup
{
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; /* Enable ADC - interrupts*/
CpuTimer2Regs.TCR.bit.TIF = 1; /* clear Timer 2 period match interrupt flag*/
CpuTimer2Regs.TCR.bit.TIE = 1; /* enable timer 2 period match interrupt*/
IER |= M_INT14; /* Enable global INT14*/
IER |= M_INT3; /* Enable global INT3*/
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;/* Enable Systemtimer 0 - Interrupt*/
IER |= M_INT1; /* Enable global INT1*/
IER |= M_INT13; /* Enable timer 1 interrupt */
}
inline void INTI_ADC_SPECIFICS(void) // called during startup; everything but ADCB removed for readability
{
EALLOW;
//write configurations
AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//delay for 1ms to allow ADC time to power up
DELAY_US(1000);
EDIS;
Uint16 acqps;
acqps = 63; //320ns
EALLOW;
// ADC B
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC will convert on channel
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3; //SOC will convert on channel
AdcbRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC will convert on channel
AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC3CTL.bit.ACQPS = acqps;
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcbRegs.ADCINTSEL1N2.bit.INT2E = 0; //disable INT2 flag
AdcbRegs.ADCINTSEL3N4.bit.INT3E = 0; //disable INT3 flag
AdcbRegs.ADCINTSEL3N4.bit.INT4E = 0; //disable INT4 flag
AdcbRegs.ADCINTSEL1N2.bit.INT1CONT = 0;
AdcbRegs.ADCINTSEL1N2.bit.INT2CONT = 0;
AdcbRegs.ADCINTSEL3N4.bit.INT3CONT = 0;
AdcbRegs.ADCINTSEL3N4.bit.INT4CONT = 0;
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 2; //end of SOC2 will set INT1 flag
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 0x14; //trigger on ePWM8 SOCB
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 0x14; //trigger on ePWM8 SOCB
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = 0x14; //trigger on ePWM8 SOCB
EDIS;
}
inline void ADC_PRESSURE_ACKNOWLEDGE() // at end of ISR
{
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;// Acknowledge interrupt to PIE
if(AdcbRegs.ADCINTFLG.bit.ADCINT1) // didn't work the first time
{
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;// Acknowledge interrupt to PIE
}
}
