Part Number:CC-DEBUGGER
Hi ,
Noted CC-Debugger-User's Guide Page 16-19
8.2 Updating the firmware manually in SmartRF Flash Programmer
loading sucessful ,but cc-debuger not recognized
8.4 Resurrecting the CC Debugger
operated software" Texas Instruments SmartRF Flash Programer"
download "EB application" ------->cebal_fw_srf05dbg.hex it is OK
but in EB booloader ,the table of EB ID can't find out device (it is null) so it can't loading files
need we change IC CC2511?
Thanks
Charlin
Part Number:PROCESSOR-SDK-AM335X
Hello
I have recently upgraded my TI SDK from 01.00.00.03 to 05.02.00.10 on our custom board based on am3352. I have modified the DTS accordingly (not really that many changes) and everything starts up as expected - well almost everything.
During powerup I get the following messages
[ 5.696014] Marvell 88E1116R 4a101000.mdio:00: attached PHY driver [Marvell 88E1116R] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[ 5.708702] net eth0: could not add device link to 4a101000.mdio:01 err -17
[ 5.725694] Generic PHY 4a101000.mdio:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=4a101000.mdio:01, irq=POLL)
[ 5.743279] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
After the system is up and running both ethernet ports is kind of working working ie i get the message
cpsw 4a100000.ethernet eth0: Link is up - 1Gbps/Full - flow control rx/tx
when conneting a LAN cable to port 0 (the phy is correctly gigbit) and when I connect a LAN cable to port 1 (which is a 100Mbps phy) i get this message
cpsw 4a100000.ethernet eth0: Link is up - 100mps/Full - flow control rx/tx
The problem is that I do not get an IP address from the DHCP server when connecting the cable to port 0 wherease I do get an IP address when connecting to port 1.
This setup previously worked perfectly in SDK 01.00.00.03 (which is a couple of revisions from SDK 5´05... I know)
Any help in resolving this mystery wil be greatly appreciated
Best regards
Kim Engedahl
/ {
model = "MPI AM335x LINKCOM";
compatible = "ti,am335x-linkcom", "ti,am33xx";
chosen {
stdout-path = &uart0;
};
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x08000000>; /* 128 MB */
};
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
wl12xx_vmmc: fixedregulator1 {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_gpio>;
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio3 18 0>;
startup-delay-us = <70000>;
enable-active-high;
};
ddr3_s3_fixed: fixedregulator2 {
compatible = "regulator-fixed";
regulator-name = "ddr3_s3";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
};
ddr3_s5_fixed: fixedregulator3 {
compatible = "regulator-fixed";
regulator-name = "ddr3_s5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&user_leds_s0>;
compatible = "gpio-leds";
led1 {
label = "lc5::ses";
gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led2 {
label = "lc5::pwr";
gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
/* Consider to enable this for activity during power-on */
/* linux,default-trigger = "heartbeat";*/
default-state = "on";
};
led3 {
label = "lc5::prt";
gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
gpio_buttons: gpio_buttons0 {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
switch1 {
label = "lc5-btn";
linux,code = <0x114>; /* BTN_EXTRA */
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
};
};
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_s0 &clkout2_pin &ddr3_s3_default &ddr3_s5_default>;
ddr3_s3_default: ddr3_s3_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* gpmc_csn1.gpio1_30, OUTPUT | MODE7 */
>;
};
ddr3_s5_default: ddr3_s5_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE7) /* gpmc_csn2.gpio1_31, OUTPUT | MODE7 */
>;
};
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8C0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_data8.gpio2_14 */
AM33XX_IOPAD(0x8C4, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_data9.gpio2_15 */
AM33XX_IOPAD(0x8C8, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_data10.gpio2_16 */
>;
};
gpio_keys_s0: gpio_keys_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8B0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* xdma_event_intr0.gpio0_19 */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart5_pins: pinmux_uart5_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE5) /* gmii1_crs.uart5_ctsn */
AM33XX_IOPAD(0x910, PIN_OUTPUT_PULLDOWN | MUX_MODE5) /* gmii1_rxerr.uart5_rtsn */
AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE3) /* gmii1_col.uart5_rxd */
AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii1_refclk.uart5_txd */
>;
};
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9B4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 (ok) */
>;
};
nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
/* Slave 2 */
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* Slave 2 reset value*/
AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
/* wl12xx/wl18xx card on mmc1. NOTE! The HW starts from mmc0 while DTS starts from mmc1 */
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x99C, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 WLAN IRQ*/
AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
>;
};
/* wl12xx/wl18xx */
w12xx_pins_default: pinmux_wl12xx_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 BT enable*/
>;
};
wl12xx_pins_sleep: pinmux_wl12xx_pins_sleep {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
>;
};
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9A0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3_18 WLAN enable */
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
tps: tps@2d {
reg = <0x2d>;
};
eeprom0: eeprom0@50 {
compatible = "at,24c256";
reg = <0x50>;
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x08000000>; /* CS0: 128MB for NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 2>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00020000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000A0000 0x00200000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x002A0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x002C0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x002E0000 0x01400000>;
};
partition@9 {
label = "NAND.rescue-file-system";
reg = <0x016E0000 0x01400000>;
};
partition@10 {
label = "NAND.file-system";
reg = <0x02AE0000 0x02800000>;
};
partition@11 {
label = "NAND.user-file-system";
reg = <0x052E0000 0x01E00000>;
};
partition@12 {
label = "NAND.settings";
reg = <0x070E0000 0x0F20000>;
};
partition@13 {
label = "NAND.downloads";
reg = <0x08000000 0x04800000>;
};
partition@14 {
label = "NAND.spare";
reg = <0x0C800000 0x03800000>;
};
};
};
#include "tps65910.dtsi"
&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;
regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};
vio_reg: regulator@1 {
regulator-always-on;
};
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
/* NOTE: Am335x EVM evaluation board schematic connects this to VDD_CORE */
/* LINKCOM V connects this to VDD_MPU */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: regulator@3 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
/* NOTE: Am335x EVM evaluation board schematic connects this to VDD_MPU */
/* LINKCOM V connects this to VDD_CORE */
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
vdd3_reg: regulator@4 {
regulator-always-on;
};
vdig1_reg: regulator@5 {
regulator-always-on;
};
vdig2_reg: regulator@6 {
regulator-always-on;
};
vpll_reg: regulator@7 {
regulator-always-on;
};
vdac_reg: regulator@8 {
regulator-always-on;
};
vaux1_reg: regulator@9 {
regulator-always-on;
};
vaux2_reg: regulator@10 {
regulator-always-on;
};
vaux33_reg: regulator@11 {
regulator-always-on;
};
vmmc_reg: regulator@12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii-txid";
};
&mmc1 {
status = "okay";
vmmc-supply = <&wl12xx_vmmc>;
ti,non-removable;
bus-width = <4>;
cap-power-off-card; /* powering off the card is safe */
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wlcore";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 3, 17 */
ref-clock-frequency = <26000000>;
};
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&wkup_m3 {
ti,scale-data-fw = "am335x-evm-scale-data.bin";
};
&gpio1 {
ti,no-reset-on-init;
};
My DTS files is
Part Number:TPS22910A
Hi,
I'm planning to use TPS22910A and TPS22913B load switch for one of my battery operated circuit.
The switch is just used to connect battery output to a resistor divider network ( battery ---TPS22910A/TPS22913B----- Resistor divider). Switch is enabled by Microcontroller GPIO.
1. Do I need to still connect an output capacitor ( C load) ?
2. Data sheet says output capacitor as optional. What is the significance of the same ?
3. What slew rate will be the switch working with no output capacitor connected ?
4. My load current is only 12-15 Micro amperes.
Thanks
Anil
Part Number:CC85XXDK-HEADSET
Hi ,
"PurePath Wireless Configurator" confige CC85XXDK-Headset ,it can make hex or bin? if it is opend ,easy to modify uncarefully and it can't go into volume production ?
can you more suggestion?
Thanks
Charlin
Part Number:CC3220
Hello,
I plan to use CC3220 as Wi-Fi engine and have to estimate its power consumption and required battery capacity.
Data is collected by another processor that will use CC3220 for communication only.
There are 2 possible scenarios:
1. "Stand alone". CC3220 is switched off or in deep sleep mode. Sensor collects data (about 1 Kbyte) and activates CC3220 once per specific period (about 15 minutes). CC3220 establish communication with server, transfers data and returns to deep sleep or shut down.
2. "Connected". CC3220 should keep minimal wi-fi connection to be able to receive command from server. If command is received, CC3220 transfers data to server (same amount of data as in "stand alone" mode) and returns to "wait for command" mode.
How can I estimate power consumption (mAh) of these two modes?
Thanks,
Yakov
Part Number:TLC59116-Q1
Hi Team,
I currently use the TLC59116 for RGB management and I want to use it to manage one power LED (white or IR).
I see in the TLC59116-Q1 datasheet (page 31) that it is possible to use several outputs for one LED.
Regarding the power LED, I want to power it at 250mA by using 5 outputs with 50mA max for each.
For I²C management, do I have to set the 5 outputs at the same value (between 0 and 255) or can I set them with different value (i.e.: out0 = 255; out1 =60; out2 = 0 ...)? It is important for me because it is linked to LED current step.
If you need additional datas, don't hesitate,
Thanks in advance for your feedback
Baptiste,
Part Number:DRA75
Tool/software: Linux
Hello all,
We are using DRA75 with vision sdk 3.04, we are getting continuous error from vdrm and kernel backtrace as below:
[17048.031079] WARNING: CPU: 1 PID: 11377 at /home/buildserver/work/jenkins/var/lib/jenkins/workspace/MMT2020_DB_Advanced_applinux/project/elina-distro/build-cpm-mmt-2020/tmp/work-shared/mmt2020-a880/kernel-source/drivers/gpu/drm/vdrm/v_crtc.c:414 v_crtc_atomic_begin+0x5c/0x60()
[17048.031090] Modules linked in: spot_memtop(O) cputop(O) tntfs(PO) texfat(PO) usb_f_ncm u_ether usb_f_fs libcomposite configfs sd8xxx mlan cfg80211 cryptoloop loop ti_fpd3_serdes smsc95xx smsc75xx asix usbnet mii usb_storage snd_soc_simple_card snd_soc_bt_sco snd_soc_mmt2020_mcasp snd_soc_edma snd_soc_omap dspipc snd_soc_omap_harman_dsp snd_soc_omap_dsp snd_soc_omap_dsp_pcm dwc3 snd_soc_core udc_core snd_pcm_dmaengine snd_pcm dwc3_omap snd_timer xhci_plat_hcd snd soundcore xhci_hcd usbcore usb_common rpmsg_proto memcache(O) silabs_dabplugin pvrsrvkm(O) omap_remoteproc rpmsg_rpc virtio_rpmsg_bus remoteproc virtio virtio_ring omap_mailbox [last unloaded: cfg80211]
[17048.031410] CPU: 1 PID: 11377 Comm: kworker/1:10 Tainted: P W O 4.4.84 #Rel_Elina_J6_MMT_18511A
[17048.031424] Hardware name: Generic DRA74X (Flattened Device Tree)
[17048.031442] Workqueue: events v_atomic_work
[17048.031457] Backtrace:
[17048.031479] [<c0015170>] (dump_backtrace) from [<c00153c0>] (show_stack+0x20/0x24)
[17048.031489] r7:600f0093 r6:c09b7c04 r5:c09b7c04 r4:00000000
[17048.031525] [<c00153a0>] (show_stack) from [<c0365ff4>] (dump_stack+0x90/0xa4)
[17048.031542] [<c0365f64>] (dump_stack) from [<c0038990>] (warn_slowpath_common+0x94/0xc4)
[17048.031550] r7:c04368e0 r6:0000019e r5:00000009 r4:00000000
[17048.031584] [<c00388fc>] (warn_slowpath_common) from [<c0038ac4>] (warn_slowpath_null+0x2c/0x34)
[17048.031593] r8:00000000 r7:00000000 r6:600f0013 r5:ee8f6b24 r4:ee8f6800
[17048.031635] [<c0038a98>] (warn_slowpath_null) from [<c04368e0>] (v_crtc_atomic_begin+0x5c/0x60)
[17048.031653] [<c0436884>] (v_crtc_atomic_begin) from [<c0409730>] (drm_atomic_helper_commit_planes+0x80/0x27c)
[17048.031661] r7:00000000 r6:c0436884 r5:00000002 r4:c3b66880
[17048.031693] [<c04096b0>] (drm_atomic_helper_commit_planes) from [<c0433cd0>] (v_atomic_complete+0x3c/0xd0)
[17048.031700] r9:ccc1d200 r8:00000000 r7:cbe0eec0 r6:ee886000 r5:c3b66880 r4:cbe0eec0
[17048.031735] [<c0433c94>] (v_atomic_complete) from [<c0433f28>] (v_atomic_work+0x18/0x1c)
[17048.031742] r7:ec068400 r6:ec061800 r5:ccc1d200 r4:cbe0eec0
[17048.031777] [<c0433f10>] (v_atomic_work) from [<c0051490>] (process_one_work+0x148/0x570)
[17048.031792] [<c0051348>] (process_one_work) from [<c005190c>] (worker_thread+0x54/0x52c)
[17048.031801] r10:ec061800 r9:ccc1d200 r8:00000008 r7:c3922000 r6:ec061814 r5:ccc1d218
[17048.031834] r4:ec061800
[17048.031851] [<c00518b8>] (worker_thread) from [<c0057bb4>] (kthread+0x11c/0x134)
[17048.031860] r10:00000000 r9:00000000 r8:00000000 r7:c00518b8 r6:ccc1d200 r5:c3df77c0
[17048.031890] r4:00000000
[17048.031908] [<c0057a98>] (kthread) from [<c0010d48>] (ret_from_fork+0x14/0x2c)
[17048.031915] r7:00000000 r6:00000000 r5:c0057a98 r4:c3df77c0
[17048.031939] ---[ end trace 628cc065562c003b ]---
[17048.032185] ------------[ cut here ]------------
[17048.032204] WARNING: CPU: 1 PID: 8064 at /home/buildserver/work/jenkins/var/lib/jenkins/workspace/MMT2020_DB_Advanced_applinux/project/elina-distro/build-cpm-mmt-2020/tmp/work-shared/mmt2020-a880/kernel-source/drivers/gpu/drm/vdrm/v_crtc.c:414 v_crtc_atomic_begin+0x5c/0x60()
[17048.032213] Modules linked in: spot_memtop(O) cputop(O) tntfs(PO) texfat(PO) usb_f_ncm u_ether usb_f_fs libcomposite configfs sd8xxx mlan cfg80211 cryptoloop loop ti_fpd3_serdes smsc95xx smsc75xx asix usbnet mii usb_storage snd_soc_simple_card snd_soc_bt_sco snd_soc_mmt2020_mcasp snd_soc_edma snd_soc_omap dspipc snd_soc_omap_harman_dsp snd_soc_omap_dsp snd_soc_omap_dsp_pcm dwc3 snd_soc_core udc_core snd_pcm_dmaengine snd_pcm dwc3_omap snd_timer xhci_plat_hcd snd soundcore xhci_hcd usbcore usb_common rpmsg_proto memcache(O) silabs_dabplugin pvrsrvkm(O) omap_remoteproc rpmsg_rpc virtio_rpmsg_bus remoteproc virtio virtio_ring omap_mailbox [last unloaded: cfg80211]
[17048.032442] CPU: 1 PID: 8064 Comm: kworker/1:4 Tainted: P W O 4.4.84 #Rel_Elina_J6_MMT_18511A
[17048.032452] Hardware name: Generic DRA74X (Flattened Device Tree)
[17048.032464] Workqueue: events v_atomic_work
[17048.032474] Backtrace:
[17048.032489] [<c0015170>] (dump_backtrace) from [<c00153c0>] (show_stack+0x20/0x24)
[17048.032498] r7:600e0093 r6:c09b7c04 r5:c09b7c04 r4:00000000
[17048.032527] [<c00153a0>] (show_stack) from [<c0365ff4>] (dump_stack+0x90/0xa4)
[17048.032543] [<c0365f64>] (dump_stack) from [<c0038990>] (warn_slowpath_common+0x94/0xc4)
[17048.032550] r7:c04368e0 r6:0000019e r5:00000009 r4:00000000
[17048.032579] [<c00388fc>] (warn_slowpath_common) from [<c0038ac4>] (warn_slowpath_null+0x2c/0x34)
[17048.032586] r8:00000000 r7:00000000 r6:600e0013 r5:ee8f6b24 r4:ee8f6800
[17048.032617] [<c0038a98>] (warn_slowpath_null) from [<c04368e0>] (v_crtc_atomic_begin+0x5c/0x60)
[17048.032632] [<c0436884>] (v_crtc_atomic_begin) from [<c0409730>] (drm_atomic_helper_commit_planes+0x80/0x27c)
[17048.032640] r7:00000000 r6:c0436884 r5:00000002 r4:c3df7580
[17048.032673] [<c04096b0>] (drm_atomic_helper_commit_planes) from [<c0433cd0>] (v_atomic_complete+0x3c/0xd0)
[17048.032682] r9:e3345e80 r8:00000000 r7:c9b3b280 r6:ee886000 r5:c3df7580 r4:c9b3b280
[17048.032715] [<c0433c94>] (v_atomic_complete) from [<c0433f28>] (v_atomic_work+0x18/0x1c)
[17048.032723] r7:ec068400 r6:ec061800 r5:e3345e80 r4:c9b3b280
[17048.032752] [<c0433f10>] (v_atomic_work) from [<c0051490>] (process_one_work+0x148/0x570)
[17048.032766] [<c0051348>] (process_one_work) from [<c005190c>] (worker_thread+0x54/0x52c)
[17048.032774] r10:ec061800 r9:e3345e80 r8:00000008 r7:cb70c000 r6:ec061814 r5:e3345e98
[17048.032810] r4:ec061800
[17048.032827] [<c00518b8>] (worker_thread) from [<c0057bb4>] (kthread+0x11c/0x134)
[17048.032837] r10:00000000 r9:00000000 r8:00000000 r7:c00518b8 r6:e3345e80 r5:c3ed1cc0
[17048.032866] r4:00000000
[17048.032882] [<c0057a98>] (kthread) from [<c0010d48>] (ret_from_fork+0x14/0x2c)
[17048.032892] r7:00000000 r6:00000000 r5:c0057a98 r4:c3ed1cc0
[17048.032918] ---[ end trace 628cc065562c003c ]---
[17048.033320] ------------[ cut here ]------------
[17048.033341] WARNING: CPU: 1 PID: 10891 at /home/buildserver/work/jenkins/var/lib/jenkins/workspace/MMT2020_DB_Advanced_applinux/project/elina-distro/build-cpm-mmt-2020/tmp/work-shared/mmt2020-a880/kernel-source/drivers/gpu/drm/vdrm/v_crtc.c:414 v_crtc_atomic_begin+0x5c/0x60()
[17048.033350] Modules linked in: spot_memtop(O) cputop(O) tntfs(PO) texfat(PO) usb_f_ncm u_ether usb_f_fs libcomposite configfs sd8xxx mlan cfg80211 cryptoloop loop ti_fpd3_serdes smsc95xx smsc75xx asix usbnet mii usb_storage snd_soc_simple_card snd_soc_bt_sco snd_soc_mmt2020_mcasp snd_soc_edma snd_soc_omap dspipc snd_soc_omap_harman_dsp snd_soc_omap_dsp snd_soc_omap_dsp_pcm dwc3 snd_soc_core udc_core snd_pcm_dmaengine snd_pcm dwc3_omap snd_timer xhci_plat_hcd snd soundcore xhci_hcd usbcore usb_common rpmsg_proto memcache(O) silabs_dabplugin pvrsrvkm(O) omap_remoteproc rpmsg_rpc virtio_rpmsg_bus remoteproc virtio virtio_ring omap_mailbox [last unloaded: cfg80211]
[17048.033584] CPU: 1 PID: 10891 Comm: kworker/1:3 Tainted: P W O 4.4.84 #Rel_Elina_J6_MMT_18511A
[17048.033594] Hardware name: Generic DRA74X (Flattened Device Tree)
[17048.033606] Workqueue: events v_atomic_work
[17048.033616] Backtrace:
[17048.033630] [<c0015170>] (dump_backtrace) from [<c00153c0>] (show_stack+0x20/0x24)
[17048.033638] r7:60070093 r6:c09b7c04 r5:c09b7c04 r4:00000000
[17048.033667] [<c00153a0>] (show_stack) from [<c0365ff4>] (dump_stack+0x90/0xa4)
[17048.033682] [<c0365f64>] (dump_stack) from [<c0038990>] (warn_slowpath_common+0x94/0xc4)
[17048.033690] r7:c04368e0 r6:0000019e r5:00000009 r4:00000000
[17048.033718] [<c00388fc>] (warn_slowpath_common) from [<c0038ac4>] (warn_slowpath_null+0x2c/0x34)
[17048.033726] r8:00000000 r7:00000000 r6:60070013 r5:ee8f6b24 r4:ee8f6800
[17048.033757] [<c0038a98>] (warn_slowpath_null) from [<c04368e0>] (v_crtc_atomic_begin+0x5c/0x60)
[17048.033772] [<c0436884>] (v_crtc_atomic_begin) from [<c0409730>] (drm_atomic_helper_commit_planes+0x80/0x27c)
[17048.033780] r7:00000000 r6:c0436884 r5:00000002 r4:c9b3b680
[17048.033807] [<c04096b0>] (drm_atomic_helper_commit_planes) from [<c0433cd0>] (v_atomic_complete+0x3c/0xd0)
[17048.033815] r9:cf113800 r8:00000000 r7:cbcc75c0 r6:ee886000 r5:c9b3b680 r4:cbcc75c0
[17048.033847] [<c0433c94>] (v_atomic_complete) from [<c0433f28>] (v_atomic_work+0x18/0x1c)
[17048.033855] r7:ec068400 r6:ec061800 r5:cf113800 r4:cbcc75c0
[17048.033884] [<c0433f10>] (v_atomic_work) from [<c0051490>] (process_one_work+0x148/0x570)
[17048.033898] [<c0051348>] (process_one_work) from [<c005190c>] (worker_thread+0x54/0x52c)
[17048.033905] r10:ec061800 r9:cf113800 r8:00000008 r7:cc014000 r6:ec061814 r5:cf113818
[17048.033931] r4:ec061800
[17048.033946] [<c00518b8>] (worker_thread) from [<c0057bb4>] (kthread+0x11c/0x134)
[17048.033955] r10:00000000 r9:00000000 r8:00000000 r7:c00518b8 r6:cf113800 r5:c9896080
[17048.033982] r4:00000000
[17048.033998] [<c0057a98>] (kthread) from [<c0010d48>] (ret_from_fork+0x14/0x2c)
[17048.034005] r7:00000000 r6:00000000 r5:c0057a98 r4:c9896080
[17048.034027] ---[ end trace 628cc065562c003d ]---
Why this error is happening ? how we can fix this ?
Thanks in advance,
Sreeju
Part Number:BQ24295
Hello,
Can you give a recommendation for a BMS that would meet the below spec's?
Application is for a 24hr battery back up system in building automation product
- using a single cell Li-ion battery with a discharge current of 100mA (estimate!).
- need to be able to recharge the battery in 24hrs, so quite low currents actually.
- original design uses an external 5V PSU and the on-board CPU of design requires a 3.3V supply.
original plan is the LP2985 (another TI device) 3V3 LDO regulator which we already have coded.
- We do not require any of the USB protocol on the BQ24295
- An IC is good for us, since it was a complete power controller, handling the charging of Li-ion with the automatic switch over the battery back-up. So, a stand-alone power controller would be ideal. but cost target is near $0.4
- We can handle some software configuration but totally stand-alone would be even more popular!
Will appreciate the input.
Regards
Linda
hi TI professor,
Recently I use timer count 1s but in real world it is 5s.Nextly I use RTC clock count 1s and it is Synchronous with 1s timer.There are two question:
1.What is the source of the timer clock? How to set if?
2.What question cause the timer count inaccurate compared with real world time?
As shown as the picture,It is the test consult.The clock_tickperiod is 10.I use the phone to count when timer timeout triggle,the phone time about 5s.
Part Number:UCC28070
Hi,team
First of all,there is no pwm.UCC28070 doesn't work .I check it one by one. I can't find the reason ,so I recalculated all parameters.And there is a new question,I can't change 'Dmax'.
If Vin=0VAC, just through the partial voltage resistance Vsense=2V, Vinac=1V, it can be measured under the condition of maximum duty cycle drive waveform.
I set fs=100KHz,Dmax=0.9 RDMAX=59KΩ . When VCC=15V Vinac=1V Vsense=2V. I find DMAX=0.66.If I set RDMAX=68KΩ（Dmax=0.95），and I test Dmax = 0.6.Why DMAX is always about 0.6. I changed a new UCC28070. DMAX also equals to 0.6.Before I recalculated parameters， I can test Dmax=0.9.
Beside these, about Nct,I calculate Nct =592. I find TI set Nct= 0 ~ 200.So I set Nct=200. Whether it is right or wrong.My Lct=84mH.
Here is my mathCAD.Could you please take a little time to check my parameter calculation right or wrong ?
Thank you！
(Please visit the site to view this file)
I have some doubts about the GPIO configuration of DS90UB947 and DS90UB948.
Our solution is: GPIO of CPU controls peripherals through 947 and 948.
Current testing: GPIO2, GPIO3, GPIO8 control peripherals of UB947, UB948 have no problems, GPIO5, GPIO6 control peripherals have problems.
UB947, GPIO5 and GPIO6 are set as input, read register 0x1c, state GPIO5 and GPIO6 are 1.
UB948, GPIO5 and GPIO6 are set as output and enable remote, and GPIO5 and GPIO6 are measured as low level.
UB948, GPIO5 and GPIO6 are set to local output, so there is no problem with the control peripheral.
Look at the datesheet with the following description:
Is it because GPIO [5-8] can't be used like this? Or is there a problem with configuration?
Part Number:CC3200
Tool/software: Code Composer Studio
Hi,
lRetVal = sl_WlanPolicySet(SL_POLICY_CONNECTION, SL_CONNECTION_POLICY(0, 0, 0, 0, 0), NULL, 0);
returns -7.
What does it mean and how to solve this issue?
Part Number:BQ24401
I'm using the BQ24401 to charge 3s NiMH batteries 3.6V 1600mAH.
I'm using a 5V input to the charging circuit this voltage drops to 4.5 though the diode.
Circuit is set up for a max current of 500mA.
Everything seems to be working ok. I'm curious about the trickle charge. I plugged a battery pack in that's been drained to 0.9V.
The trickle charge begins and seems to be working but it seems to bring the battery back to a certain point then it can't get past it.
The voltage at the BAT pin is between 608-650mV and the battery voltage is up to 1.8-2.0V. You can see the current on the 5v line pulsing at 50mA.
It has been on for 18 hours.
Is there something in the circuit I can adjust to get the trickle charge to push past this point and kick into fast charge?
Thought about increasing the Rmto to even out the duty cycle a little I currently have a 39.2K and Cmto is 0,15uF.
Please advise.
Part Number:LM5145
Hi,
just want to check if it's OK that BST-GND is -1.6V/5.986uS when do Vout short test since datasheet mentioned -0.3V spec.
Part Number:DS90UB947-Q1
Hi team
My customers wants to apply DS90UB947 + DS90UB948 for the TFT LCD solution.
DS90UB947 is LVDS_D[0:7] and LVDS_CLK as input spec.
LVDS spec supported to AP that they used is as below.
- Resolution: 1920*1080p
- Pixel Clock: 40~160MHz
- LVDS_D[0:4] : 5Lane Data
- LVDS_CLK : 1Lane Clock
Input lane is not same.
Is it ok to design DS90UB947 + DS90UB948?
If not, please suggest me another solution.
Thank you.
Part Number:CC1101
Hi Team,
I need some example code about mbus communications or knx communications.
Regards,
Fabio
Part Number:66AK2L06
Hi,
We set up Optimized Radar System Design Using 66AK2L06 and ADC14X250.
We were able to sample analog signal in high speed with 66AK2L EVM.
We have achieved I and Q data separately of input analog signal. But we do not need I and Q values. We need digital value of Analog signal.
And we think it may be related some of this files : Lamarr_DFE_1xLTE80_HC_245p76_JESD121_121x_CDFRsum_noCFRnoDPDe_lane0_v2.bin and aid_PLAYBACKFULL_1xLTE80_Demo2_NoNPswap.out
( @ 66AK2L06-Design-Demo_RFSDK_02.00.03.00-DEMO2_01.00.00.tar.gz\usr\share\radio\demo2_pack\dsp\Lamarr-lte80-demo2 )
Is it possible to see source files of this files ?
Part Number:DP83849IF
Hi,
I am using DP83849 evaluation board from TI as a media converter board & I am not using MCU.
PORTA --> RJ45
PORTB --> Fiber Optic
I have made the below Jumper settings as mentioned in tidu510a.pdf. However, I am not sure if I need to connect the MII signals between PORTA & PORTB to implement the media conversion.
Do we really need to loopback MII signals( RXD[3:0] to TXD[3:0] ) or does the PHY make the connection internally?
Best Regards,
Yash
Part Number:LM5145
Hi,
based on datasheet, SS/TR should be stable after power up until power down or fault happens. But during transient test, it seems SS/TR also goes down when Vout goes down. Please kindly check.
Part Number:TLV320AIC3106
Tool/software: Code Composer Studio
Hello, My EVM is
and, reading and writing by I2S mode.
For the Real-time sound pre-processing and recognition in ccs,
By selecting just one of the inputs for Left and another for Right (in a single-ended mode), I can have one channel from MIC and one channel from LINE IN.
the graph of the each channel(32bit 48kHz) is below( I2S mode / Mcasp)
To get spectrogram and another digital processing in Real-time(ONLINE),
I just want audio waveform data such as 
How to convert TDM Mode(I2S Mode) data(PCM data) to "Audio Waveform data"??
Any advice and suggestion please...
Regards,
