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TMS320F28034: Temperature Sensor Minimum Sample Window Requirement

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Part Number:TMS320F28034

In the "Silicon Errata",the "Temperature Sensor Minimum Sample Window Requirement " is 550ns,but we found 150ns is OK.
So I want to know if i need to change the it from 150ns to 550ns.


TPS22975: TPS22975 Rising time calculate request

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Part Number:TPS22975

Hi Team

       I want adjustable rise time. TPS22975 Datasheet P.15  Vout rising time formula  is Vbias =5V.

         SR = 0.43 * Ct +  26 

But my Vbias = 3.3V.

         How did I calculate the slew rate ?  same Calculation formula ? 

RTOS/CC1310: How much longer is the time needed in one loop with TIRTOS than without RTOS if implementing the same function

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Part Number:CC1310

Tool/software: TI-RTOS

Dear Sir or Madam: 

          My project is to implement wireless microphone function with CC1310 , and it is strictly in time delay about RF communication.

So I want to know How much longer is the time needed  in one loop with TIRTOS than without RTOS if  implementing  the same function?

Thanks a lot!

TPS659037: Inrush current LDO1 and LDO2

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Part Number:TPS659037

Hi all

Would you mind if we ask TPS659037?

<Question1>
There is the description "Inrush current LDO1 and LDO2" on the datasheet P15,
Why do only LDO1 and LDO2 show inrush current?
Because of big current regulation?

<Question2>
In relation to <Question1>, how much is LDOLN's inrush current?


Kind regards,

Hirotaka Matsumoto

Linux/TDA2: #pragma DATA_SECTION to UTILS_HEAPID_DDR_CACHED_SR

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Part Number:TDA2

Tool/software: Linux

Hi:

 i  am  useing   SDK_VISION_03_04_00_00\vision_sdk  

in   a   dsp1 link    i   want   put    my  model   to  UTILS_HEAPID_DDR_CACHED_SR, 

#pragma DATA_SECTION (model,UTILS_HEAPID_DDR_CACHED_SR );

MInt32  model[] =
{
    177, 301, 176, 321, 176, 340, 177, 359, 180, 379, 184, 398, 189, 417, 195, 435, 202, 453, 212, 471, 223, 487, 235, 502, 249, 516, 263, 529, 278, 541, 294, 553, 311, 562, 331, 568, 352, 569, 374, 566, 396, 558, 414, 547, 431, 533, 446, 519, 460, 504, 473, 488, 484, 470, 493, 451, 499, 431, 503, 412, 506, 392, 507, 373, 508, 353, 507, 334, 506, 314, 504, 294, 501, 275, 199, 272, 215, 257, 235, 253, 256, 255, 276, 260, 290, 274, 272, 273, 254, 270, 236, 268, 218, 269, 356, 267, 370, 251, 392, 243, 415, 238, 438, 238, 459, 250, 438, 252, 417, 255, 396, 260, 376, 265, 223, 308, 232, 302, 242, 298, 254, 297, 266, 299, 276, 305, 282, 314, 273, 316, 263, 318, 253, 319, 242, 317, 232, 314, 373, 305, 381, 294, 391, 287, 404, 284, 417, 284, 428, 286, 438, 293, 429, 300, 419, 304, 408, 307, 396, 307, 384, 306, 307, 302, 309, 337, 306, 373, 289, 391, 298, 412, 327, 415, 347, 413, 377, 406, 382, 384, 363, 368, 355, 333, 352, 298, 280, 461, 300, 451, 324, 443, 343, 444, 362, 438, 388, 440, 413, 445, 396, 463, 375, 476, 349, 483, 322, 482, 299, 475, 286, 462, 315, 460, 345, 458, 376, 452, 407, 447, 377, 455, 346, 461, 315, 462, 253, 309, 406, 296, 328, 301, 330, 332, 332, 362, 334, 391, 337, 414, 253, 307, 409, 294,
};

can  i ?

Shuai

66AK2H12: Relationship between MPAX of MSMC and EDMA transfer

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Part Number:66AK2H12

Hi,

I have qestion about EDMA transfer vis MSMC.

In "Example_Application_Layout" below, DDR3(0x81000000 - 0x81FFFFFF) is mapped as private data area of Core0-3.

In the above setting, when data is transferred from DDR3(0x81000000 - 0x81FFFFFF) to the global L2 SRAM of each core by EDMA, which physical address of DDR3 is actually referenced?
In this example, since the source address setting of PaRAM of EDMA is all the same, I want to know which data is being transferred.

For example, will it be transferred as follows;

EDMA transfers data form DDR3(0x81000000 - 0x81FFFFFF) to the global Core0 L2 SRAM : Data of physical address (0x8_01000000) is transferred?
EDMA transfers data form DDR3(0x81000000 - 0x81FFFFFF) to the global Core1 L2 SRAM : Data of physical address (0x8_02000000) is transferred?
EDMA transfers data form DDR3(0x81000000 - 0x81FFFFFF) to the global Core2 L2 SRAM : Data of physical address (0x8_03000000) is transferred?
EDMA transfers data form DDR3(0x81000000 - 0x81FFFFFF) to the global Core3 L2 SRAM : Data of physical address (0x8_04000000) is transferred?

Best Regards,
H.U

MSP430FR6989: LCD character #5 not working

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Part Number:MSP430FR6989

Hello, 

I was given a bord by a TI employee to work with and upon running the startup demo I noticed that the 5th character has three segments not working. When I attempt to have it output an "8" I get a reverse "C" instead. This means the left vertical segments as well as the middle horizontal segment are not working. Is there anything that could cause this besides a LCD failure, broken resistor or other intermediary IC that could be changed. 

Thanks

Kas

DRV8323R: DRV8323RH - PWM mode logic??

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Part Number:DRV8323R

Hi,

I have designed motor driver with DRV8323RH and 1xPWM mode is used.

I have thinked driver works well because motor rotates well.

But I found a strange things recently.

So I check them with BOOSTXL-DRV8323RH with TI GUI.

when GHA is pwm, GHB and GHC should low in the logic table.

But, GHB is low and GLB is low.

GHC is high and GLC is low(<-- strange)

so MOT_C is VM,

I attached the signal and experimet set-up

Could you check this?

I think it is related to previous question.(https://e2e.ti.com/support/motor-drivers/f/38/t/723387)

<experiment set up> hall sensor is connected and motor ABC wire is not connected.



GHA(YELLOW), GHB(CYAN), GLB(MAGENTA)

GHA(YELLOW), GHC(CYAN), GLC(MAGENTA)

MOT_A(YELLOW),  MOT_B(CYAN), MOT_C(MAGENTA)

TI EVM GUI (10% duty is applied, VM is 30V)


CCS/TM4C1294KCPDT: Eclipse system variables in command line

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Part Number:TM4C1294KCPDT

Tool/software: Code Composer Studio

I am trying to create a variable loaded with the contents of windows system variable %computername%.

The previous thread  suggests inserting a flag -DHOSTNAME=%COMPUTERNAME% into the project properties - ARM Compiler.
That doesn't seem to work:

-D__HOSTNAME__=%COMPUTERNAME%
expands as a command-line string:
--define=__HOSTNAME__=%COMPUTERNAME% 
and when referenced as
strcpy(p_txBuffer,__HOSTNAME__);
I am getting error: "../ipb_dbg_uart.c", line 1359: error #29: expected an expression.

During debugging I tried defining the string without using the system environment variable - just to try what may be wrong.
both --define=HOSTNAME=MY_MACHINE or --define=HOSTNAME="MY_MACHINE" yield error #20: identifier "MY_MACHINE" is undefined.
Clearly - the double quotes are "eaten away" in the process.

After lengthy experimenting I got my project build when I escaped the double quote marks:
--define=HOSTNAME=\"MY_MACHINE\"

However, --define=__HOSTNAME__=\"%COMPUTERNAME%\" returns the string "%COMPUTERNAME%" without the substitution for the environment variable.

What am I missing here?

Thanks! Martin

TMDSCNCD28379D: TMS320F28379D MCU pin allocation

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Part Number:TMDSCNCD28379D

Hello TI officers,

I am using the TMDSCNCD28379D Delfino controlCARD. As stated in the schematic file and the BOM file, it is using the MCU TMS320F28379D with package ZWT 337 pins. But the 180-pin HSEC docking station board only allows me to access to a maximum of 180 pins of the MCU. So where are all the other pins ( 157 pins) routed to ? Why don't I have access to them ? 

If I want to make my own break-out board with the MCU TMS320F28379D, is it necessary to route all 337 pins to external headers ? 

Regards,
An.

WEBENCH® Tools/WEBENCH-POWER-DESIGNER: does WEBENCH support thermal simulation

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Part Number:WEBENCH-POWER-DESIGNER

Tool/software: WEBENCH® Design Tools

Dears

I can't find any thermal simulation in WEBECH

where can I find them, thanks

TLV320AIC3204: TLV320AIC3254 fs setting.

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Part Number:TLV320AIC3204

Dear Sir,

My customer using digital microphone (fCLK) spec. is 1.2MHz,

If would like support 8KHz sampling rate, which register need setting?

Thanks, Ian.

LM5036: 500W Isolated DC/DC converter request

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Part Number:LM5036

Hi,

For the request:

500W isolation DC/DC conveter - plan to use Boost and DC/DC controllor for 19Vin/12Vout 40A.

1. Does LM5036 suitable for this spec? Or any suggested solution?

2. For Boost controllor, is there any suggestion?

Thank you.

CCS/TMS320F28069: TMS320F28069

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Part Number:TMS320F28069

Tool/software: Code Composer Studio

I tried running a given example by Control Suite in CCS v8.2.

I tried to build the given example project I imported.

The following errors were the given result. How to overcome these errors?


1. --cdebug_asm_data is no longer supported --cdebug_asm_data is no longer supported 


2. gmake: *** [Example_2806xGpioSetup.obj] Error \

CCS/CC2640R2F: offset & gain parameters about AOA

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Part Number:CC2640R2F

Tool/software: Code Composer Studio

Hello,

        I recently debugged the offset & gain parameters of AOA.

        I find those parameters description by BLE-STack User's Guide,and is there a specification for offset & gain debugging rules?

        Thank you very much.


TM4C1290NCPDT: RTOS/TM4C1290:When using RTOS UART Driver, how to set UART Interrupt FIFO Level Select

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Part Number:TM4C1290NCPDT

Hello,

I am using TI-RTOS Drivers to UART. (TI-RTOS 2.16)

I want to change Interrupt FIFO Level Select.

I have tried UARTFIFOLevelSet API after UART_open().

my code:

 //RTOS UART Drivers
 UART_Params uart_params;

 UART_Params_init(uart_params);
 up->baudRate  = 500000;    //boudrate 500kbps
 up->readDataMode = UART_DATA_BINARY;
 up->writeDataMode   = UART_DATA_BINARY;
 up->readReturnMode = UART_RETURN_FULL;
 up->readEcho  = UART_ECHO_OFF;
 up->readTimeout = 100;

 uart = UART_open(Board_UART6, &uart_params);

 //Peripheral Driver Library UART API.
 // UARTIFLS register is Interrupt FIFO Level Select.
 // RX FIFO 1/8 to 1/2(UART_FIFO_RX4_8)
 UARTFIFOLevelSet(UART6_BASE, UART_FIFO_TX1_8, UART_FIFO_RX4_8);


The result showed that UARTIFLS(UART6 UARTIFLS:0x40012034) register value changes 0x00000000 to 0x00000010.

Is this the right approach?
Or is there another right way?

Thanks.

MSP430FR2522: Captive touch sensor pattern guideline for FPC(Flexible Print Circut).

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Part Number:MSP430FR2522

Hi ,

      Customer layout captive touch  button on FPC board as below picture. The performance is so bad. I think it because the board is too thin cause the parastic cap too much.

  • They are asking  a layout guideline for  FPC board. 
  • Do we have other customer using captive touch  in FPC and success? 
  • Self  or mutual, which one is best for this application.

B.R.

Jeff Chen

TMS320F280049: Updating code via bootloader without cutting off the power stage output

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Part Number:TMS320F280049

Hi team,

I am writing to check can we support functions like updating code without cut off the PWM output?

One of our customer is evaluating C2000 in their server PSU project. They require code updating via CAN, which can be realized by customized bootloader. The key point is they need the MCU to remain basic control function, and keep the output of the PSU during the updating.

In our new F28004x devices, you actually stressed we can write to one flash while reading/executing from the other one. Can we realize the requirements I mentioned above with this feature? We are meeting more and more similar demands in our digital power customers.

Thanks for you support!

TUSB522P: What is the shortest distance on post channel

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Part Number:TUSB522P

Hi Sirs,

Sorry to bother you.

As title, 

1. What is the shortest distance on post channel for our layout?

2. Could you help double review our schematic? any suggestion are welcome.

(Please visit the site to view this file)

66AK2L06: IPC_messageq: Cannot read property "base" from undefined

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Part Number:66AK2L06

Hello Champs,

Customer created a IPC_messageq project, there is an error message " Cannot read property "base" from undefined" when building the project. 

Below is the config.bld and ipc.cfg code. 

config.bld:
var SR_0 = {
        name: "SR_0", space: "data", access: "RW",
        base: 0x84800000, len: 0x200000,
        comment: "SR#0 Memory (2 MB)"
    };
ipc.cfg.xs
var SR0Mem = Program.cpu.memoryMap["SR_0"];
SharedRegion.setEntryMeta(0,
    newSharedRegion.Entry({
        name:           "SR_0",
        base:           SR0Mem.base,
        len:            SR0Mem.len,
        ownerProcId:    1,
        isValid:        true,
        cacheEnable:    xdc.global.SR0_cacheEnable
    })


Thanks.
Rgds
Shine

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