Part Number:CCSTUDIO

Tool/software: Code Composer Studio

hi,

I need VISION SDK  2.8, 2.9:  VISION_SDK_02_08_00_00, VISION_SDK_02_09_00_00

Radar SDK 2.12, 3.1:  PROCESSOR_SDK_RADAR_02_12, PROCESSOR_SDK_RADAR_03_01_00_00

Where can I download these ? I have CCS V7.1.0.00016  for TDA3x (DSP: TMS320C66x)..

Thanks

Rafi

Part Number:AM5728

Tool/software: Linux

Hi,

I'm using processor SDk 4.02 and trying to get a non-root Linux to boot in a jailhouse cell on cpu 1. Has any work been done on this already as wiki only describes RTOS or bare metal examples?

Thanks, Iain

Part Number:AFE4900

Hi team,

I have a customer who uses the AFE4900 in a shipping product and they are trying to add firmware updates. They asked me how they might be able to tell if the sensor is or isn't in contact with a human body. I cannot see the datasheet so I can't see the register map. They are asking for any example code we might have written that we could pass along to give them the jist of how to do it. If that isn't available, an explanation of how they might pull that off using existing status registers would be appreciated. 

Feel free to take this offline with me if info is sensitive.

Thanks,

Brian 

Part Number:BQ76940

Hello,

We are developing a battery module which employs bq76940 + bq78350 + MSP430 in LiFePO4 battery energy storage system. After this thread (e2e.ti.com/.../2471248, we did not have the results as expected, even changing some balancing parameters. Then, we would like try an algorithm made by ourselves in order to improve balancing, minimizing battery capacity loss. 

For this task, we need to command manually all balancing FETs through bq78350-r1. For this reason we have some doubts:

1-) Reading bq78350-R1 technical reference, we assume ManufacturerAccess() could be used to control balancing FETs. However, we did not find any command to accomplish this control. Is it really feasible control those FETs trough bq78350?

2-) If it is not feasible, this control should be accomplished directly through I2C interface by MSP430 controller, in my opinion. Is there any issue related on this circuit? We are worried it may have some data collisions, because the MSP430 e bq78350 may want access bq76940 at same time.

3-) If you need to access AFE trough MSP, do you have a sample code? I read a application note related to this topic, but, I have found any source code on website.

Thank you in advance.

Best regards,

Part Number:LMP90078

What are the electrical characteristics for this part with Buffer off?  The table 8.5 shows only specs with Buffer ON.  How can we find the equivalent specs with Buffer OFF?

Part Number:ADC12D1600QML-SP

I am evaluating ADC12D1600CCMLS for use on a NASA mission that requires microcircuits to conform to EEE-INST-002 Level 1 (section M3). Although the ADC12D1600QML-SP part number family contains the term "QML", it does not have a 5962* part number so it's unclear which MIL-PRF-38535 QML class the flight part conforms to (if any). Therefore it is unclear what testing is performed for screening and qualification.

Screening: I need to know whether each test listed below is performed as a part of the standard screening flow for ADC12D1600CCMLS, and what test method [e.g. from MIL-STD-883] is used. I have seen the TI document called "Testing and Inspection of QML Class Q Ceramic Devices" which shows the screening flow diagram for Class M and Class B devices, but I haven't seen any documentation showing that ADC12D1600CCMLS conforms to the screening flow in that document. I need confirmation whether the tests listed below are performed on 100% of parts in every lot of ADC12D1600CCMLS parts. Hoping you could send me a sample screening traveler or a sample of a screening record that’s already been filled out for a past lot.

• Wafer lot acceptance
• Nondestructive bond pull
• Internal visual inspection
• Temperature Cycling
• Constant acceleration (e.g. centrifuge)
• PIND
• Radiographic inspection
• Serialization
• Initial Electrical measurements
• Burn-in
• Final electrical measurements
• Delta between initial and final electrical measurements
• Percent defective allowable (is there a limit for a manufactured lot?)
• Hermetic seal: Fine leak, Gross leak
• External visual

Qualification: TI technical support sent me a document called "FMQR New Package Qual ADC12D1620" which has some information. The document shows records of these qualification tests for ADC12D1600CCMLS:

• Resistance to solvents
• Bond strength
• Die attach strength (shear test)
• Solderability
• Life test, 1000 hours
  

I need to know whether these remaining EEE-INST-002 Level 1 qualification tests were ever done for qualification, and what test method [e.g. from MIL-STD-883] was used. Or perhaps are these done as screening tests as a lot-based qualification?

• Hermetic seal: Fine leak, Gross leak- Was ADC12D1600CCMLS perhaps qualified via a different part number’s package?
• Thermal Shock
• Temperature Cycling
• Moisture resistance - Was ADC12D1600CCMLS perhaps qualified via a different part number’s package?
• Shock
• Vibration
• Constant acceleration (e.g. centrifuge)
• Residual Gas Analysis and/or Internal Water Vapor - Was ADC12D1600CCMLS perhaps qualified via a different part number’s package?
• Adhesion of lead finish - Was ADC12D1600CCMLS perhaps qualified via a different part number’s package?
• Lid torque - Was ADC12D1600CCMLS perhaps qualified via a different part number’s package?

Part Number:TPS54331

Tool/software:TINA-TI or Spice Models

PROBLEM

Buck converter design was made to operate with minimum input voltage of 5V. However, the lower limit is showing bad results on the startup of the buck converter TPS54331 (datasheet).

OBSERVATIONS

Figure 1 shows part of the schematic with the problematic circuit.

• Buck converter is not starting when super capacitor is charged. It was observed a relation between super capacitors voltage Supercap and input voltage, when:
  • Supercap voltage 3.50V, buck startup Vin 5.2V.
  • Supercap  voltage 2.90V, buck startup Vin 5.05V.
  • Supercap  voltage 2.50V, buck startup Vin 4.70V.
  • Issue is more likely to happen at 85°C.
    • The board starts at 5.6V when the super capacitors are with 3.22V.

The circuit was simulated with different parameters using TINA Software. However, none of them worked fine, and, the IC is not working with 5V input voltage, it starts the operation at 5.84V on the software.

Using the online tool to select power supply in TI website (WEBENCH) they recommend the use of TPS54331, for this very same application.

START UP ONLY

When applied 7V to the input and this voltage is slowly decreased, buck converter keeps operating until the external undervoltage diables the EN pin, at 4.45V.

ENABLE PIN

There is a recommendation to use external VIN UVLO to add hysteresis when VIN is lower than Vout + 2V. However, as we are applying 2.8V directly through an inverter port to this pin, the IC is activated.

VOUT LIMITATIONS

Since the converter has a limit on minimum and maximum duty cycle. These limit values are calculated and they are within the duty cycle range.

RL=35mΩ

VD=0.7V

IOmax=Iomin=3ARds(on)max = 200mΩ

VIN(MIN)=5V

VO(MAX)= 3.85V

The Maximum Output Voltage (VO(MAX)) of 3.85V is the higher output voltage that the IC can deliver with a 5V input voltage. So, 3.52V is within the output voltage range and it is ok.

Temperature might cause some variations on these resistance and diode drop, however, the circuit was not tested with this maximum output current (IOmax), but 300mA, which will result in a VO(MAX) of 4.44V.

Part Number:LM5032

I have a customer who is trying to LM5032 to produce a high powered converter. See his remarks:

We are in the process of developing a 2KW Standby Power Inverter for Emergency Lighting. The main Power Board is comprised of:

A PFC Boost Converter to charge up the +/- 190 Volt Bus while On Line.

A charger circuit to Charge the batteries while on Line (using one of the Boost Inductors)

An Inverter to Convert the +/- 190 Volt Bus to 120 VAC while On Line and On Battery.

An Interleaved Boost circuit to Convert the Battery Voltage to +/- 190 while On Battery.

The Attached Schematic shows the Interleaved Boost circuit components.

For Initial testing, only the components associated with L7 and L9 were loaded. (half the Power Devices). Also, Q3 was replaced with the same SIC diode as D12.

I have been testing for several weeks to obtain the best results with 3 circuit boards.

This has involved:

Different values for the current feedback resistors R60, R65 and capacitors C40,C44.

Different combinations of Snubbers for the Power Fets and Diodes.

Different filtering for the Power Supplies.

Different Gate resistors for the Fet Drivers.

Different values for the voltage feedback circuit of U10, C48,R51 and C47.

The attached picture #1, shows the current waveform at CS1, with the voltages across FETs. This is at 1800 watt load, and is interleaving properly with little current ripple measured at the Battery.

The attached picture #2 shows an identical loaded board, but not sharing properly.

I have tested different boards, under load conditions from 200 watt up to 3000 watts. Sometimes it works properly under light load but not heavy load, or vice versa. I had concluded that this is due to the high frequency (120 mhz) noise on the current feedback at CS1 and CS2. I attributed it to the switching Power Devices and Inductors.

I loaded a new board with only the LM5032 components and power supply. The current feedback resistors R60 and R65 tied to ground with 12 resistor.

The attached picture #3 and 4 shows waveforms at CS1 and Out1. The high frequency ringing is present at rising falling edges of each output and at CS1. I have tried different power supply filtering and even substituted the power supply DC-DC converter with a Battery and no change.

Any ideas on how to suppress the ringing at the CS pins?

Is this normally what is seen?

I feel if this ringing wasn’t so large the circuit would work well.

I did not want to post the schematic, but I can send it to you along with the scope shots that are referenced below. Please let me know if you can look at this and try to find the issue.

Thanks for your help with this!

Richard Elmquist

Part Number:DLPDLCR2010EVM

Hello,

I have three questions:

1) I want to run four EVM on a single computer. Is it possible to run four separate instances of the DLP Lightcrafter Display GUI on a single computer?

2) I want to project a unique still-frame image with each projector. Is the best solution to update the firmware on each projector with the desired image, or run a still image over HDMI using the video command?

3) Can the EVM module be powered on without an optical engine present?

Thank you,

Dan

Part Number:MSP430F5659

Team,

My customer has the following question:

We are currently working on a project that will use the MSP430F5659 and we intend to use its USB capabilities. I have done some initial research, and I believe LithiumWerks can use TI's USB VID for free and get a PID assigned to us by TI (also free) provided that we don't use the USB logo on our product and that we use an MSP430. Can you confirm this?

Also, what RTOSes can you recommend for the MSP430F5659 that either already have USB support or integrate well with your USB stack?

Thanks,

Brian

Part Number:TPS2660

Hello,

In another e2e thread, it was advised that:

"It is OK to leave SHDNb pin unconnected if you are not using the Shutdown functionality. But please note that the internal pullup is very week and need to consider external pullup if you require rugged operation."

I'm looking for some clarification around the term "rugged".    Is there a concern that noise injected into this node may cause undesirable operation?

Don

Part Number:ADS7953

For added diagnostic on a PCBA I like to add several ADS7953 (15pcs).

Is it possible to reduce the interface pin count to the controller (FPGA). For example connect all CLK lines, SDI and SDO lines to three FPGA pins and 15 CS selections pins. This would reduce the pin count on the FPGA from 60 to 18.

A sample rate of 1Hz for each input is enough for diagnostics purposes.

Taking SI in to consideration: one bus line, no/short stubs to the ADCs pins.

Part Number:TCI6638K2K

Tool/software: Linux

We are using the HPLIBMOD kernel module for DDR memory allocations in ARM and for data transfer from ARM to DSP.  We are facing the problem that the data written from ARM is not seen correctly at DSP side, as DSP application is still reading out the old values from the DDR memory. For DSP implementation, we do use the L2 invalidate function before reading from the DDR memory location.  For ARM side, we do use hplib_cache.h header file (mcsdk_linux_3_01_04_07_syslib4/linux-devkit-rt/sysroots/cortexa15t2hf-vfp-neon-linux-gnueabi/usr/include/ti/runtime/hplib/hplib_cache.h) that does provide the hplib_cacheWbInv() type of functions.  In this file, we see that the cache functions are empty unless CORTEX_A8 is defined by the user ARM application.

Accordingly, we have defined CORTEX_A8 in our ARM application.  C6638 on the other hand does have Cortex A-15.  May you clarify what is the correct way to use the cache operations with HPLIBMOD kernel module on C6638 ARM core Linux application?

Part Number:TCA9617B

Hi,

I'm using the TCA9617B as a level shifter between Aardvark (3.3V level) to a Slave device (1.8V level).Since side B can't support 1.8V level I connected the Slave device to Side A and the Master device to Side B.Is it a valid connection? What would be the recommanded typical pull-up resistors for using 800K speed?

Regards,

Matty  

Part Number:UCC28251

How does the UCC28251 create the deadtime from one leg to another? 

 I am using this UCC28251 for the Push-pull application and we are seeing differences from the deadtime on one leg compared to the other (A to SRA Tdps = 225ns vs B to SRB Tdps =  300ns).  I know the PWM has a wide tolerance for Tdsp and Tdps but my assumption would be that the deadtime of one leg would be the same for the corresponding deadtime of the other leg.

Thanks!

Russell

Part Number:TMS320F28377S

Tool/software: TI C/C++ Compiler

Wrong MISRA-C :2004 warning:

../main.c", line 73: warning #1483-D: (MISRA-C:2004 12.6/A) Expressions that are effectively Boolean should not be used in operations with expressions that are not effectively Boolean

Code for reproducing:

typedefunsignedintu16_t;

voidtestme(u16_t u16_tv);

typedefstruct {

u16_tau16_test[6];

u16_tu16_tw;

} ST_Test;

ST_Test mast_test[3];

voidtestme(u16_t u16_tv)

{

mast_test[0].u16_tw = u16_tv + 0u;

mast_test[0].u16_tw = u16_tv;

}

/**

* Application entry point

*/

voidmain(void)

{

testme(23u);

}

Full build output:

**** Build of configuration Debug for project boot ****

"D:\\ti\\ccsv8\\utils\\bin\\gmake" -k -j 4 all -O

Building file: "../main.c"

Invoking: C2000 Compiler

"D:/ti/ccsv8/tools/compiler/ti-cgt-c2000_18.1.1.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -O0 --opt_for_speed=2 --include_path="C:/Users/L029453/DSPbase2/ti_boot" --advice:performance=all -g --c89 --relaxed_ansi --diag_warning=225 --diag_wrap=off --display_error_number -k --asm_listing --check_misra="all,-1.1,-2.2,-5.7,-11.3,-17.4" --preproc_with_compile --preproc_dependency="main.d_raw" "../main.c"

"../main.c", line 73: warning #1483-D: (MISRA-C:2004 12.6/A) Expressions that are effectively Boolean should not be used in operations with expressions that are not effectively Boolean

Finished building: "../main.c"

Building target: "boot.out"

Invoking: C2000 Linker

"D:/ti/ccsv8/tools/compiler/ti-cgt-c2000_18.1.1.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -O0 --opt_for_speed=2 --advice:performance=all -g --c89 --relaxed_ansi --diag_warning=225 --diag_wrap=off --display_error_number -k --asm_listing --check_misra="all,-1.1,-2.2,-5.7,-11.3,-17.4" -z -m"boot.map" --stack_size=0x200 --warn_sections --reread_libs --diag_wrap=off --display_error_number --xml_link_info="boot_linkInfo.xml" --rom_model -o "boot.out" "./adc.obj" "./bootF2837x.obj" "./devsys.obj" "./flash.obj" "./gpio.obj" "./main.obj" "./ramcheck.obj" "./wdog.obj" "../linkerF2837x.cmd"

<Linking>

Finished building target: "boot.out"

Part Number:TLC59401

I would like to know the thermal resistance (C/W) between the junction and the thermal pad on the TLC50401, RHB package.

Part Number:ADS1115

Dear all,

I have a device that I want to measure its IV curve, the range of the voltage that this device works on is from -3 to 3 V as a maximum, so I produce a ramp voltage from 0 to 3 V using MSP430FR6989 and connect it to a RC filter as in the attached figure, then I connect LM324 opamp to have the bipolar range of the signal from -3 to 3 v, finally the device is connected to the opamp's output, until here everything is fine but once I connect the AN1 of the ADS1115 (connected to pi) to the device the negative side of the opamp's output drops from -3 to -1 V.

I replaced this opamp with TL084CN and I'm still have the same problem.

I connected another opamp as buffer but it does not work.

Also, I reduced the range of the signal to be in the range of -1 to 1 V , here I do not see a cutoff of the negative side of the waveform but I got a wrong curve.

The GND of the ADS is connected to the analog circuit with the GND of the MSP then I separated the GND of the MSP and the ADS from the analog circuit.

Could you please explain to me if this ADS is capable of reading a negative voltage or not, I read in many documents it reads from 0 to 5 V, does that mean peak to peak range? by mean if the signal is from -2.5 to 2.5 V is that ok?

The other thing I'm looking for is the common input voltage of the opamp, if someone can explain this point for me I will appreciate that.

Thank you,

Part Number:CC3220

Hi,

I'm trying to figure out what the exact procedure is to execute a host driven factory reset on the CC3220.

The simplelink programmer's guide () is not very clear on this.

As far as I can tell, with SOP[2:0] fixed on 000, I should just run the following code:

_i32 slRetVal;
SlFsRetToFactoryCommand_t RetToFactoryCommand;
_i32 Status, ExtendedStatus;
RetToFactoryCommand.Operation = SL_FS_FACTORY_RET_TO_IMAGE;
Status = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_RESTORE, 0, NULL , (_u8 *)&RetToFactoryCommand ,
sizeof(SlFsRetToFactoryCommand_t), NULL, 0 , NULL );
if ((_i32)Status < 0)
{
/*error*/
//Status is composed from Signed error number & extended status
Status = (_i16)Status>> 16;
ExtendedStatus = (_u16)slRetVal& 0xFFFF;
break;
}
//Reset
sl_Stop(10);
//sl_Start(NULL, NULL, NULL);
//CC3220
 PRCMHibernateCycleTrigger();

But is this all? Is this supposed to fully execute the entire factory reset?

From what I can see, this seem to do -something-, but after a while seems to reset the device which then fully hangs. (nothing happens/boots. Nor the old or current image)
Even when unpowering/repowering and waiting a long time, nothing seems to happen.
Only when I toggle the RESET line, after 10+s the system seems to reboot into a valid image again.

Is this behavior to be expected? And/or what is the full procedure to execute a host-driven factory reset? Am I missing something, since the toggling of the reset was not outlined in the datasheet?

Thanks for any clarification.

Arnout

Part Number:ADS8568

Dear TI,

I have attempted to design a circuit for the ADS8568 and would appreciate a review and design guidance.

My design goal for this is to use the parallel interface to a microcontroller and sample from 8 channels simultaneously at maximum speed. Input signals are in the range 0-3.3V centered at 1.65V.

My main worries:

1. On each analog input, I have this circuit which only has 49.9 ohms of resistance and a 10nF capacitor. I will probably replace the 10nF capacitor with 4.7nF to get the -3dB frequency above the sampling rate, but would appreciate any recommendations. My understanding is that this amplifier must be powered after the ADC. Should I add an extra resistor to limit current into the ADS8568? Is the extra input filtering capacitor unhelpful due to the internal capacitance?
   
2. What power sequencing is required? Right now my ±5VB supplies become active two seconds after AVDD and DVDD, is this okay?
3. Can I operate this device with ±4-VREF and a 2.5V reference from this ±5V HVDD/HVSS supply or do I need more overhead?
4. My read is that the RESET line needs to be held low in normal operation. This is flipped from most RESET lines so I wanted to confirm before hardwiring.
5. Should I instead use a choke on DVDD rather than a 10 ohm resistor?
6. Should there be a 10uF capacitor in addition to the 100nF capacitor for HVDD and HVSS?
7. I am going to use the PM version without the pad underneath. Are there recommended ground plane connections in this situation? Should I avoid running any traces under the chip and leave that as a continuous ground plane?