SM320F28335-EP: ADS1278 Interface

September 5, 2019, 9:10 pm

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Part Number: SM320F28335-EP

Hi, I am using SM320F28335-EP as my controller and interfacing ADS1278 ADC through McBSP of controller. I have some queries which I posted on data converter forums on the below link  

I have inserted my schematic screenshot. I have interfaced 2 ADS1278 with SM320F28335 controller as mentioned above. My questions are: 

Q1. SM320F28335(My controller) will act as Master in SPI and ADS1278 will act as slave.

Q2. Also my SPI is on McBSP A of controller. So will it be fine?

Q3. What about the chip select pin of McBSP, as ADS1278 is having DRDY pin. the way I have connected it to GPIO23,is it fine? Will it be able to handle that, or I should use a separate pin for DRDY.

As shown in screenshot the GPIO 21,GPIO 22,and GPIO23,i am using these pins for SPI interface. Kindly have a look.(Please visit the site to view this file)

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CCS/TMS320F28335: How to generate two different frequency EPWMs

September 5, 2019, 9:12 pm

≫ Next: TPS7A88: Feedback Resistor Values

≪ Previous: SM320F28335-EP: ADS1278 Interface

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Part Number: TMS320F28335

Tool/software: Code Composer Studio

Dear Sir/Madam,

I would like to generate two different frequency PWM using EPWM module. For example EPWM1, EPWM2 with 20kHz and EPWM3,4 with 100kHz frequency.  Please suggest somebody how to generate.

TPS7A88: Feedback Resistor Values

September 5, 2019, 9:19 pm

≫ Next: AWR1443BOOST: Can AWR1443 Boost be used for Vita Signs?

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Part Number: TPS7A88

Dear, Sir.

My customer is considering to set the freedback resistor values, R1/R2, R3/R4, to

be more smaller values for the fine tuning of output voltage.

The datasheet described the current though R2, R4 > 5uA.

1) Is it no problem to set more smaller values, R1/R2, R3/R4 to maitain >5uA?

2) I suppose the side-effect would be current consumption through the resistor divider

    network. I wonder it was correct?

3) If you find other side-effect or concern, Please let us know.

Please give your advice.

Best Regards,

H. Sakai

AWR1443BOOST: Can AWR1443 Boost be used for Vita Signs?

September 5, 2019, 9:24 pm

≫ Next: TIDA-00290: PoE PSE Type 2 (30W) IEEE 802.3at Fully Autonomous Quad Port Solution

≪ Previous: TPS7A88: Feedback Resistor Values

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Part Number: AWR1443BOOST

Good Day ~

I follow the "vitalSignsLab_xwr1443_QuickStartGuide.pdf" to set up my AWR1443Boost

and use the UniFlash 5.0 with "mmwave_industrial_toolbox_3_6_2\labs\lab0002-vital-signs\lab0002_vital_signs_pjt\Prebuilt_binaries\xwr14xx_vitalSigns_lab_mss.bin" to flash it.

Why always shown "Aborting flashing of specified files!!!" message?

 

 

Is the AWR1443BOOST not available for Vita Sign?

Or is there a problem with this version of the xwr14xx_vitalSigns_lab_mss.bin file?

 

 

Thanks ~

 

 

TIDA-00290: PoE PSE Type 2 (30W) IEEE 802.3at Fully Autonomous Quad Port Solution

September 5, 2019, 9:46 pm

≫ Next: MSP430F5514: About BSL6 Errata

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Part Number: TIDA-00290

We would like to know, the Board “PoE PSE Type 2 (30W) IEEE 802.3at Fully Autonomous Quad Port Solution, TIDA-00290” can set the PMA ELECTRICAL SPECIFICATIONS test mode. We are looking the generate the 100 and 1000BaseT PMA test mode with Power (PoE Type-1 and Type-2).

Example of PMA ELECTRICAL signal as PMA PEAK DIFFERENTIAL OUTPUT VOLTAGE AND LEVEL ACCURACY, MAXIMUM OUTPUT DROOP, DIFFERENTIAL OUTPUT TEMPLATES, MDI RETURN LOSS , TRANSMITTER TIMING JITTER, FULL TEST (EXPOSED TX_TCLK) , MASTER/SLAVE mode configuration, TRANSMIT CLOCK FREQUENCY ,COMMON-MODE OUTPUT VOLTAGE etc.

 

For each ETHERNET speed (10 ,100 of 1000 Mbps) there is IEEE spec, which defines the Physical Medium Attachment (PMA) specification. This standard of tests verifies several of the electrical specifications example as the 1000BASE-T Physical Medium Attachment sublayer outlined in Clause 40 of the IEEE 802.3 TM standard.

In this Tests, DUT (divide under test) generates the predefine test mode signal as per IEEE specification on output RJ45 port of DUT. This test signals are been measured by Tek oscilloscopes for measuring the parameters define in spec to validate. Now, we are looking for DUT, which can generate such test case signal + Power as well (PSE). PSE DUT ( test signal + Power) will connect to Power Device (PD) and we want to performance test in such setup environment, where Test mode signal as well as PD power is also present on line.

MSP430F5514: About BSL6 Errata

September 5, 2019, 9:55 pm

≫ Next: TPA6211A1-Q1: SHUTDOWN pin left open

≪ Previous: TIDA-00290: PoE PSE Type 2 (30W) IEEE 802.3at Fully Autonomous Quad Port Solution

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Part Number: MSP430F5514

Hello,

 

Regarding to BSL6(USB suspend/reset) on MSP430F5514 errata, my customer is asking a question.

 

(Question)

If this failure occurs, is there possible that password access is failed at USB BSL?

They face issue when USB_BSL_GUI.exe is run, sometimes internal flash memory is rewrite to all x0FF.

(They think that this issue is occurred by password access failure with something cause.)

As one of possible cause, do you think there is possible in BSL6 errata?

(The core revision which they use is H.)

 

Regards,

Tao 2199

TPA6211A1-Q1: SHUTDOWN pin left open

September 5, 2019, 10:03 pm

≫ Next: CCS/TMS320C6415: unable to get proper sync between cores

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Part Number: TPA6211A1-Q1

Hi team,

nSHUTDOWN pin has 100k ohm pull-down resistance.

Is it designed so that the device kept in shutdown mode without external pull-down resistance, when this pin is kept open? 

Best regards,

CCS/TMS320C6415: unable to get proper sync between cores

September 5, 2019, 10:20 pm

≫ Next: DAC5682Z: DAC5682Z & LMK04828

≪ Previous: TPA6211A1-Q1: SHUTDOWN pin left open

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Part Number: TMS320C6415

Tool/software: Code Composer Studio

In qmss project, I am pushing decsriptors from one core and popping from the other core. When I run the group core, It starts popping the descriptors but not wait for the descriptors to be pushed. How to solve this ???

Regards.

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DAC5682Z: DAC5682Z & LMK04828

September 5, 2019, 10:21 pm

≫ Next: AM26LS32A: Absolute Maximum Junction Temperature

≪ Previous: CCS/TMS320C6415: unable to get proper sync between cores

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Part Number: DAC5682Z

Hi Team,

Attached my answer.

Thanks,

Shlomi

(Please visit the site to view this file)

AM26LS32A: Absolute Maximum Junction Temperature

September 5, 2019, 10:23 pm

≫ Next: TDC1000-C2000EVM: #tdc1000

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Part Number: AM26LS32A

Hi Team,

My Customer is looking for the AM26LS32AID absolute maximum junction temperature, can you share your inputs on this?

Regards,

-Renan

TDC1000-C2000EVM: #tdc1000

September 5, 2019, 10:25 pm

≫ Next: CCS/DM3730: DSP, EDMA,L3

≪ Previous: AM26LS32A: Absolute Maximum Junction Temperature

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Part Number: TDC1000-C2000EVM

Hello,
I have been working with the TDC1000-C2000EMV with the TDC1000-C2000EVM GUI v1.2.0.83. I have some doubts. In the TOF_ONE_SHOT command tab 3 records are delivered: 1.- START TO STOP1 (us), 2.- C2000 RESULT, and 3.- OVERFLOW COUNT.
I have reviewed the TDC1000-C2000EVM User Guide, I have also reviewed the TDC1000 Ultrasonic Detection Application Data Sheet (AFE) for level detection, flow detection, concentration detection and proximity detection ( Rev. B), and in other documents. But I haven't found information describing these three records, so I don't know what each number delivered means. I need to know about these records, especially what does C2000 RESULT represent?

CCS/DM3730: DSP, EDMA,L3

September 5, 2019, 10:26 pm

≫ Next: AM5718: unexpect inter byte delay in continuous SPI transmition

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Part Number: DM3730

Tool/software: Code Composer Studio

Hi,

I'm facing a L3 in-band error when I use EDMA to copy data from GPMC to SDRAM in DSP.

my processor is DM3730.

this issue occur when DSP code enable a EDMA transfer, and there is no complete callback return, even no error.

check the IVA2.2 system port L3 register, the value is :

L3_IA_COMPONENT : 0x10106331
L3_IA_CORE : 0x200001
L3_IA_AGENT_CONTROL : 0x3e040400
L3_IA_AGENT_STATUS : 0x1000a010
L3_IA_ERROR_LOG :0x84001400
L3_IA_ERROR_LOG_ADDR : 0x0

GEM_AGENT_STATUS : 0x28

EDMA_AGENT_STATUS: 0xa3832

the register value indicate that:

1‘ there is a in-band error in L3_IA_AGENT_STATUS. 

2' EMDA agent is in a request outstanding status.

3' GEM agent is in a waiting response status.

my problem is 

1/ how could be this issue happen? did I need to reduce the L3 bus access?

2/ when this issue happen, what need I do to get the EDMA working right again?

Thanks.

AM5718: unexpect inter byte delay in continuous SPI transmition

September 5, 2019, 10:28 pm

≫ Next: CCS/TMDSEMU110-U: TMDSEMU110-U (XDS-110 USB Debug Probe) Not Detected on PC

≪ Previous: CCS/DM3730: DSP, EDMA,L3

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Hello everyone,

I'm facing the problem that there is unexpect inter byte delay in continuous SPI transmition on AM5718 SOC.

SPI1 controller works in master transmit only mode, the SPICLK speed is 24MHz, word length is 8 bit, POL0_PHA0, turbo mode.

Total SPI frame length is 64 byte,  CS is controlled by software. 

EDMA is used in the transmition, and SPI slave can receive data correctly.

BUT when watching the SPI bus timing,  we find that there is unexpect inter byte delay in continuous SPI transmition.

SPICLK is 24M, the delay between two bytes is 82ns(turbo off mode is 100+ns).

The delay makes the SPI transmit bandwith lower than idea.

How to remove or reduce the delay?

Can anyone give me some help, thanks a lot.

Part Number: AM5718

CCS/TMDSEMU110-U: TMDSEMU110-U (XDS-110 USB Debug Probe) Not Detected on PC

September 5, 2019, 10:28 pm

≫ Next: CCS/TMS320F28335: CCSv6 and XDS510USBPlus

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Part Number: TMDSEMU110-U

Tool/software: Code Composer Studio

Hello,

I recently purchased the TMDSEMU110-U  USB debug probe for Debugging/ Programming  an Active Front end Controller which uses a Texas Instruments TMS320F28335 DSP.

When I Connect my XDS 110 USB Debugger (TMDSEMU110-U) to the JTAG Terminal of the Board, The USB probe is not visible/detected in CCS V9 as well as the Windows Device Manager.

Only the GREEN LED of the TMDSEMU110-U glows when connected to the PC Via USB.

I have tried using different USB Cables and also tried to connect the USB probe in CCS V9  using LInux OS (Xubuntu 18.04) but the TMDSEMU110-U  is not being detected there as well.

Please Assist.

Regards,

Meenakshi

CCS/TMS320F28335: CCSv6 and XDS510USBPlus

September 5, 2019, 10:31 pm

≫ Next: CCS/TMS320F28379D: ePWM

≪ Previous: CCS/TMDSEMU110-U: TMDSEMU110-U (XDS-110 USB Debug Probe) Not Detected on PC

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Part Number: TMS320F28335

Tool/software: Code Composer Studio

I have the Code Composer v6 installed and linked to the Simulink Support Package. When I use the Texas Instruments Docking-Stn USB-EMU [R3] to program the F28335 everything works well but when doing the same with the Texas Instruments Peripheral Explorer [R-5] I cannot program the F28335. I have read this is due to an inner problem of the Explorer that has the USB-SCI Tx-Rx signals crossed. Therefore, I have tried to connect to the JTAG via the Digital Spectrum XDS510 USB Plus Emulator, and to program it via CCSv6 with the code generated by the Simulink. However, the CCSv6 seems not to work with the Emulator. Is there any way to do this in a simplified way?

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CCS/TMS320F28379D: ePWM

September 5, 2019, 10:34 pm

≫ Next: PCM2900C: Suspend Pin configuration

≪ Previous: CCS/TMS320F28335: CCSv6 and XDS510USBPlus

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Part Number: TMS320F28379D

Tool/software: Code Composer Studio

Hello i have written a code for PWM in cpu timer. I have encountered a error which i am not able to understand. Kindly help.

The error is :

10:54:21 **** Clean-only build of configuration CPU1_RAM for project cpu_timers_cpu01 **** make clean  Cannot run program "make": Launching failed  Error: Program "make" not found in PATH PATH=[C:/ti/ccsv7/eclipse/jre/bin/client;C:/ti/ccsv7/eclipse/jre/bin;C:/ti/ccsv7/eclipse/jre/lib/i386;C:\Program Files (x86)\Intel\iCLS Client\;C:\Program Files (x86)\Common Files\Oracle\Java\javapath;C:\ProgramData\Oracle\Java\javapath;C:\Program Files\Intel\iCLS Client\;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\WINDOWS\System32\WindowsPowerShell\v1.0\;C:\Program Files\MATLAB\R2018a\runtime\win64;C:\Program Files\MATLAB\R2018a\bin;C:\WINDOWS\System32\OpenSSH\;C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\DAL;C:\Program Files\Intel\Intel(R) Management Engine Components\DAL;C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\IPT;C:\Program Files\Intel\Intel(R) Management Engine Components\IPT;C:\Users\Admin\AppData\Local\Microsoft\WindowsApps;;C:\ti\ccsv7\eclipse;]  10:54:21 Build Finished (took 168ms)   **** Build of configuration CPU1_RAM for project cpu_timers_cpu01 ****  Nothing to build for project cpu_timers_cpu01

PCM2900C: Suspend Pin configuration

September 5, 2019, 10:35 pm

≫ Next: TPS7A83A: No External Bias, Bias pin floating or connecting to a capacitor?

≪ Previous: CCS/TMS320F28379D: ePWM

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Part Number: PCM2900C

Hello,

We have a query about the Audio Codec PCM2900C.

In our design we are not using HID pins and SUSPEND mode so what should be the configuration for SUSPEND pin for us?

Regards,

Bankesh

TPS7A83A: No External Bias, Bias pin floating or connecting to a capacitor?

September 5, 2019, 10:43 pm

≫ Next: TMS320C6678: PCIe configuration for multicore real scenario

≪ Previous: PCM2900C: Suspend Pin configuration

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Part Number: TPS7A83A

Hello Team,

May I confirm with you that with no external bias, the correct connection of bias pin is floating or connecting it to a capacitor?

In Figure 48. ANY-OUT Configuration Circuit (no external bias) the bias pin connects to a external capacitor; however in 6.3 Recommended Operating Conditions note (3) it said If BIAS is not used, a capacitor on the BIAS pin is not needed. But I am not sure best connection to bias pin when there is no external bias.

Thank you!

Regards,

Ting

 

TMS320C6678: PCIe configuration for multicore real scenario

September 5, 2019, 10:44 pm

≫ Next: DLPC200: Unused PORTx_Dx operation

≪ Previous: TPS7A83A: No External Bias, Bias pin floating or connecting to a capacitor?

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Part Number: TMS320C6678

Hi,

    Having 2 TMS320C6678 devices connected through PCIE and all 8 cores activated, I have some questions regarding the pre-setup before using PCIe transfers from all/to 8 cores.

1. Pcie_init(), pciePowerCfg(), Pcie_open(), SerDes configuration should be executed by core0 only, or must be run from all 8 cores? As "Pcie_Handle" obtained after Pcie_open() call is specific to every core, I think it should be executed an every core, but what about rest of the mentioned APIs?

2. What about BAR masks? It is sufficient to do this only from one core and all others to use these BARs directly without configuring again?

3. Configuration of the OB_SIZE, Gen2 speed, inbound and outbound regions - should these configurations to be done by only one core or every core should configure its own inbound/outbound regions and to use it exclusively?

Let's suppose that I configured one inbound  region from core0 and I provided to ibCfg.ibOffsetAddr a global variable specific to core0. How I should use the same PCIe inbound region from core1?

I am forced to use exclusive pairs of regions and cores (like configure inbound region0 for BAR1 when I run from core0 and configure region1 from BAR1 when I run from core1, ....) or I should use for "ibCfg.ibOffsetAddr" a buffer from the shared memory to be able to use the same inbound region from many cores? Or I could use both variants?

Thank you.

DLPC200: Unused PORTx_Dx operation

September 5, 2019, 10:44 pm

≫ Next: [TDA4M] Test Description of UDMA datasheet

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Part Number: DLPC200

Hello TI members,

DLPC200 datasheet recommends unused PORTx_Dx should connect  to 10kΩ pulldown. However, my customer is asking whether something of problems occur if unused PORT1/2_D0-23 are directly connected to GND. Do you have any comments regarding direct connection to GND?

Regards,

Uryyy