Part Number: ADC104S021

Page 5 describes T_CLH as the hold time between SCLK Low (which I assume means the falling edge) to CS_N Falling Edge.  The timing diagram (Figure 5, Page 7) Shows t_CLH to be the delay between the falling edge of CS_N and the rising edge of SCLK.  Which is correct?  Are there any limitations on the SCLK falling edge to CS_N falling edge timing?  A previous E2E answer ("ADC124S051-timing of SCLK and CS") implied there are none (is it a spec sheet typo, or am I wildly confused).

Thank you,

Brett

Part Number: LSF0101

team,

we need to look for a buffer/level shifter that has one output which is open-drain, and one output which is push-pull and meets the MDIO/MDC electrical requirements, can you advice if LSF0101 ok to use?  

or any other recommend?

Part Number: CC1310

Hi,

My customer needs to certify radio modules (CE RED) using CC1310 as for SubGhz and CC2642R for BLE.

Customer needs to accelerate this certification process.

For BLE there are some docs in ti.com, but for SubGhz I could not find anything. For SubGHz customer is using for SW part the EasyLink libraries.

I think customer would need a document like "How to Qualify Your Bluetooth® Low Energy Product" but for SubGhz.

Do you have comments here?

Many Thanks,

Antonio

Part Number: OPT3001

According to the datasheet OPT3001 should match human eye frequency response. I designed a board using OPT3001 with IR LED from OSRAM (SFH 4770). OPT3001 is used for sensing if there is enough visible light to switch on/off IR LED for security camera. However when IR LED is turned on the OPT3001 immediately return numbers about 3500 lux whereas with LED off it is reporting 300 lux. From what I see frequency response is nowhere near the advertised in datasheet (LED is 850nm). Is there anything I need to configure in the driver to change the frequency response to reject IR light?

Thank you in advance.
Stepan

Part Number: AM5746

Hi,
My customers may fail USBD_bulkWrite.
We are currently working on a solution to this phenomenon.

Question 1:
We want to investigate this issue, but we can't find information about DWC3.
Would you provide information about the DWC3 userguide and registers map?
They are using USB_open (1,…) USB1 ("DWC3_1").

Question 2:
We don't know how to debug if USBD_bulkWrite fail.
Which registers (descriptor) should we look at?

Question 3:
I posted about the relationship with Eratta i819 before.
e2e.ti.com/.../833095
They saw the i819 workaround and modified the code.

C:\ti\pdk_am57xx_1_0_11\packages\ti\drv\usb\src\dwc\usb_dwc_dcd.c

Line:301
// HW_WR_FIELD32(dwc3->baseAddr + DWC_USB_DCFG, DWC_USB_DCFG_DEVSPD,
// DWC_USB_DCFG_DEVSPD_HS);
HW_WR_FIELD32(dwc3->baseAddr + DWC_USB_DCFG, DWC_USB_DCFG_DEVSPD,
DWC_USB_DCFG_DEVSPD_SS);

However, USBD_bulkWrite () fail.
Would you tell me specific examples of correction.

Question 4:
e2e.ti.com/.../833095
We don't understand what exactly happens to Eratta i819.
What phenomenon will happen?
Is this i819's trigger that "connect/disconnect the USB cable"?

ENV
　AM5746 Customer's board
　pdk_am57xx_1_0_11
　bios_6_76_00_08

　DWC3 as USB2.0

Regards,
Rei

Part Number: TDA3MV

Hi,

I am working on a project with TDA3 SR2.0. We use both M4 cores, DSP, EVE, ISP, DSS, LDC, CSI-2.
First I noticed the errata "i882 EMIF: DDR ECC Corrupted Read/Write Status Response" and thougth that in SR2.0 ECC will work fine. Yesterday I activated the ECC in our EMIF driver for the bootstrap. After that the software that normally boots did not boot properly. M4_1 did not start or had an exception, I don't know. After disabling the ECC booting was ok, again.

Than I found the application note "ECC/EDC on TDAxx" sprac42b

I was surprized that there is a restriction to access the DDR3 with activated ECC.

"EMIF supports ECC on the data written or read from the SDRAM. Enable the ECC feature by writing to
the appropriate registers inside the EMIF subsystem. ECC accesses are allowed for both SYS and the
MPU ports. 7-bit ECC is calculated over 32-bit data when in 32-bit DDR mode. 6-bit ECC is calculated
over 16-bit data when in 16-bit DDR mode. The ECC is calculated for all accesses that are within the
address ranges protected by ECC. These address ranges are software configurable. The ECC must be
enabled and only aligned writes with byte count in multiple of 4 bytes (2 bytes for narrow mode) should be
used. This is true for all TDA devices other than TDA2PX where you can have sub quanta writes as well."

"2.5.1.1 Restrictions Due to Non-Availability of Read Modify Write ECC Support in EMIF
In normal mode, a 7-bit ECC is computed for each 32-bit word, whereas, in narrow mode, a 6-bit ECC is
computed for each 16-bit word. EMIF does not provide read-modify-write support for ECC for all TDA
devices except TDA2PX. This means that any sub-quanta write access (less than 32 bit for normal and
less than 16 bit for narrow mode) generates an incorrect ECC and writes it into ECC memories. Any
further reads to such corrupted regions will very likely generate false 1-bit or 2-bit errors. To ensure this
does not happen, software design should take care of the following points."

To be sure...so in the end, if an unaligned write access by the M4 occured, reading of this same address later generates an 1-bit or 2-bit error event and the read value is corrupted. Is it right?
I assume in case of 2-bit error the value should be correct, cause of no wrong correction?

I know, there are some complex workarounds for M4 and DSP in case of cached or non-cached variants. In case of EVE the solution to handle the ECC restriction is in software possible, only. And devices like DSS or EDMA have to follow the restriction of 32bit alignement accesses.

Is it realy a good idea to check and modify the whole software to avoid unaligned write accesses? What about SYS/BIOS? Is it prepared for this ECC restriction?

I think it is more likely that an unaligned access remains undetected, than an ECC error happens. So another solution would be to use DDR3 with integrated ECC functionality.

What do you thing about it?

Best regards,
Milan

Part Number: ADC104S021

I am trying to save pins in my project.  One option I'm considering is to try to run the ADC104S021 without active CS_N control (either by hard tieing it to ground, tieing it to a power-up reset chip, or by tieing it to a one-shot triggered by the falling edge of SCLK).  To this end, I have two questions:

1) Assuming I have properly synched myself to the stream, can I continuously read the device by sending 16 bit clocks (and appropriate DIN configuration messages) without ever toggling the CS_N line?

2) Will the chip reset automatically if I let SCLK go idle for a period of time even if CS_N is constantly asserted?  How long?

Thank you,

Brett

Part Number: TPS61088

Hello TI, 
             We are using BQ24773 Charging IC for 1S Lithium Polymer battery on Input adapter 5V/5A

Battery output voltage is 3.7V
Continuous System Load is 5V/5A 
Expected Battery charger Output voltage is 5V

1.When the Adapter is OFF and Battery power to load what is Maximum output Voltage and current ..?
2.When the Adapter is ON and battery is not preset what is the Maximum Output voltage and current ..?
3.When Both supply source on what is the Maximum Output voltage and current ..?

Thanks and Regards, 
Rahul Surawase

Part Number: AMIC110

Tool/software: Code Composer Studio

Hi there,

I'd like to switch between the release and the debug version of the PDK_am335x_1_0_13 library. I created the two versions using gmake all BUILD_PROFILE = debug / release.
The CCS continues to use the release version regardless of whether I set the build configuartion to debug or release. How can I convince CCS to generate a debug version?
Best regards
Thomas

Part Number: IWR1642BOOST

Tool/software: Code Composer Studio

I am getting maximum 10m of range using iwr1672boost. What is the maximum range that i can achieve using the demo code? and how do i achieve it?

Part Number: LMK04808

Tool/software: WEBENCH® Design Tools

Hi TI experts,

LMK04808B has two PLLs. The VCO of PLL1 is an external VCXO or a tunable Crystal. 

However, the entry to specify the frequency of VCXO is not found the WeBench Clock Architect design tool. Instead, the Clock Architect generate a configuration solution of LMK04808B with a specified VCO frequency of the PLL1.

If a VCXO with the frequency other than the auto-generated PLL1 VCO frequency, for example the 122.88MHz VCXO in  LMK04808BEVAL, is picked, how can I still use the WeBench Clock Architect design tool to optimize the design of two filers in LMK04808?

Best Regards!

Wallace

Part Number: BQ24773

Hello TI 

            What is the Maximum Output voltage & Current of BQ24773 at 5V/5A Input adapter..?

            Required register setting to get max rating as mention ..?

Thanks for your valuable answer 

Thanks and regards, 
Rahul Surawase

Part Number: TMS320F2811

Tool/software: TI C/C++ Compiler

I want to run my program completely out of RAM. At startup, the code is copied from Flash memory to RAM.

My program has grown large enough such that it will not fit in the 8K contiguous H0 area.

Is there some way I can arrange for part of the code to be transferred to the H0 area and part of the code to be transferred to another area (L0, for example) as part of the startup process?

I have targeted the TMS320F2811.

Part Number: AMC1210

Hello I use the AMC1210 chip paired with the ADS1205 to measure the rotation angle of the transformer(RESOLVER). I have the following questions:
1) Can I get the initialization order of the AMC1210 chip.
2) Can a AMC1210 interaction with stm32 SPI be obtained.
3) When measuring the maximum value of data stored in the register AMC1210 the value of channel 1 is constantly different from the value of channel 2. At that, the same signals are supplied to channels. What could it be related to?

Part Number: DP83867CS

Hello,

We are using this PHY chip on our custom board with NXP LS1046A SoC (ARM64). Our board has 4 Ethernet interfaces, all using TI's DP83867CS as PHY and connected via SGMII to the SoC.

The problem is that no link is detected at all, after plugging in the cables. One of the cable is company's network cable and the other one is connected to a second NIC in a regular office PC. They both are working using NXP's Devkit for this SoC (they use different PHY though). But in case of our PCB - the link is not detected (I can see that in PHY's registers and on the PC).

I can communicate via MDIO from the U-Boot, I can read registers - I confirmed that SGMII is enabled in the registers, that link is not detected and that auto-negotiation is enabled but not completed. TI's U-boot driver for DP83867CS is enabled, compiled and loaded by the U-Boot.

Do you know what could be the cause? Can you confirm that link should be detected even without any software configuring PHY in any way?

I attach the schematic (we've found some bugs, marked with red crosses, that we corrected on the PCB by removing those elements).

Part Number: AM3352

Hi,

We are trying to port from U-boot V2013.10 to V2018.01 and Kernel from V3.2 to V4.14.

Hardware remains the same.

TI SDK Used: V05.03.00.07.(Please visit the site to view this file)

Hardware Info:

Processor is AM3352 and it is interfaced to parallel NOR flash from Cypress (part number :S70GL02GS) via GPMC CS0.

Cypress guys provided an excellent support and here is the full discussion from the bootloader till the kernel problem. (First part of the discussion is on U-boot and next is on Kernel).

 https://community.cypress.com/message/206271#206271

 We have successfully ported u-boot and all features are working at the u-boot level.

 NOR flash info from u-boot:

=> fli

Bank # 1: CFI conformant flash (16 x 16) Size: 256 MB in 1024 Sectors

AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E4801

Advanced Sector Protection (PPB) enabled

Erase timeout: 2048 ms, write timeout: 1 ms

Buffer write timeout: 3 ms, buffer size: 512 bytes

 Other commands erase and cp are working at u-boot level.

Problem Statement:  We have problem in bringing the NOR flash up in kernel. 

Old Kernel (3.2.0): All below commands did not work as expected. No concept of dts here and we have .config file.

        cat /proc/partitions

        ls -la /dev/mtd*

        mtdinfo

        mount

        mtd_debug info /dev/mtd0

My modifications in new Kernel

• Applied the patch provided by Cypress team.
• Updated the DTS per hardware (I have attached GPMC changes).
• In new kernel, I have enabled all MTD related configuration except for enabling CONFIG_MTD_CHAR (because this option is not available in new kernel). 

Observation 1:

Since CONFIG_MTD_CHAR is not available in new kernel and to understand the importance of CONFIG_MTD_CHAR, I have disabled this configuration in the old kernel and tested:

Below commands are not working.

       cat /proc/partitions

        ls -la /dev/mtd*

        mtdinfo

        mount

        mtd_debug info /dev/mtd0

     CONFIG_MTD_CHAR is a must parameter.    

Observation 2:

In old kernel mtdchar.c is being compiled based on CONFIG_MTD_CHAR. 

In the new kernel drivers/mtd/mtdchar.c is being compiled even though we don’t have CONFIG_MTD_CHAR enabled, it is taken care if CONFIG_MTD is enabled.

Additional changes:

Since code was not entering "drivers/mtd/chips/cfi_probe.c", I have enabled MTD_PHYSMAP_OF and tested.

I have attached kernel configuration of old and new kernel.

Please find attached kernel log file for old kernel (working) and new kernel (not working).

Can you please let me know what is that I am missing?

If you need any more input from my side please let me know.

Regards

Srinivasa

Part Number: TIDA-00792

Hi,

I have designed a BMS using BQ78350-R1, BQ76940 AFE and Bq76200 Mosfet Driver and my BMS is nearly the same as TIDA-00792 Reference Design. The Li-Ion battery pack with this BMS is working properly, everything about the battery pack is well. However, I have designed this battery pack for AGV (Automated Guided Vehicle) device. The AGV is operated by Lead Acid Battery without any problem but it is not operated by our Li-Ion battery pack. When we monitors the motor drivers inside the AGV using motor driver interface, drivers cut off the output because of the Over Voltage Alert. However, output of the battery pack is never cut off.

I think, in this case It is necessary to explain, the AGV' s motor drivers generate electric energy and it wants to charge it back to battery pack. (regenerative system). I am concerning that the problem arises from here. Because when I read the datasheet of the motor drivers, it says that the electric energy generated by motor drivers must be charged to battery pack or consumed across a shunt resistor.

Do you have any suggestion to solve problem or experience about that?

Thanks in advance.

Part Number: IWR1642BOOST

Tool/software: Code Composer Studio

I want hard coded configuration of srr code how do i do it?

Part Number: LAUNCHXL-CC26X2R1

Dear,

I was testing the CC26x2 launchpad with my niece and the following code:

/*
 * 
 */

/*
 *  ======== uartecho.c ========
 */
#include <stdint.h>
#include <stddef.h>

/* Driver Header files */
#include <ti/drivers/GPIO.h>
#include <ti/drivers/UART.h>

/* Example/Board Header files */
#include "Board.h"
uint8_t n;
/*
 *  ======== mainThread ========
 */
void *mainThread(void *arg0)
{
    char        input;
    const char  echoPrompt[] = "Echoing characters:\r\n";
    UART_Handle uart;
    UART_Params uartParams;

    /* Call driver init functions */
    GPIO_init();
    UART_init();

    /* Configure the LED pin */
    GPIO_setConfig(Board_GPIO_LED0, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_LOW);

    /* Turn on user LED */
    GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON);

    /* Create a UART with data processing off. */
    UART_Params_init(&uartParams);
    uartParams.writeDataMode = UART_DATA_BINARY;
    uartParams.readDataMode = UART_DATA_BINARY;
    uartParams.readReturnMode = UART_RETURN_FULL;
    uartParams.readEcho = UART_ECHO_OFF;
    uartParams.baudRate = 115200;
    uint32_t timeoutUs = 3000000;
    uartParams.readTimeout = timeoutUs / 10;
    uart = UART_open(Board_UART0, &uartParams);

    if (uart == NULL) {
        /* UART_open() failed */
        while (1);
    }

    GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON);
    n = UART_read(uart, &input, 1);
    GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF);


    /* Loop forever echoing */
    while (1) {
        UART_read(uart, &input, 1);
        UART_write(uart, &input, 1);
    }
}

It is very similar to one of your examples uartecho.c.

We can see if we leave the RXD jumper on the Launchpad closed, the code does work. We can observe a 3 seconds LED approximately.

If you open such jumper, the code does NOT work. The LED blinks few milliseconds.

Why is this? How can we obtain the same 3 seconds expected blocking behavior somehow with both cases?

Thanks.

Part Number: IWR1642

Hi,

I read TI has a policy of 12 months notification before end-of-life.

Do we get this notification by mail after clicking on 'Alert me' on the chip webpage ?

For people counting, Justin Curewitz told me that:

« We recommend moving to IWR6843 as that is the device that will be receiving continued support. »

https://e2e.ti.com/support/sensors/f/1023/t/827484?tisearch=e2e-sitesearch&keymatch=%2520user%253A414316

Does it mean, in a way, that TI is already planning to discontinue the IWR1642 ?

Best regards,

Massimo