Part Number:DS90UB941AS-Q1

Dear TI Experts,

Can DS90UB941 support DP to FPDLINK?

From the datasheet,it can support DSI to FPDLINK

I'd like to know whether it can support DP to FPDLINK, If not, do you have any other solutions?

Looking forward to your help.Thank you very much ~

Part Number:AM5726

Hi,

I am considering a gateway for industrial communication. I want to realize this in one chip.
Is there a device that can realize the following functions with Sitara in one chip?

1. EtherNet/IP Master + EtherNet/IP Slave + EtherCAT Master + EtherCAT Slave
2. EtherNet/IP Master + EtherCAT Master
3. EtherNet/IP Slave + EtherCAT Slave
4. Standard TCP/IP + EtherNet/IP Master + EtherNet/IP Slave
5. Standard TCP/IP + EtherCAT Master + EtherCAT Slave

Can each combination mentioned above be realized with AM57xx?
Also, is there a possibility that can be realized with AM335x or AM437x?

Best Regards,
H.U

Part Number:DS32ELX0421

Hi,

Could you please tell me how to configurate DS32ELX0421 and DS32ELX0124? And the configuration content of these two chips?

Thanks.

Kevin Xiong

Part Number:AM5728

Hi everyone,

I can not find TMDXIDK5728's web page.

Is the TMDSIDK574 a substitute?

Part Number:TMS320DM368

hi there ! 

i have been trying to run H.264 encoder with leopard imaging board LI-TB02 using DM368 with ridgerun demo image for TVP5146 composite input. 

here is my gstreamer pipeline

gst-launch -v v4l2src input-src=composite chain-ipipe=true always-copy=false queue-size=6 ! 'video/x-raw-yuv,format=(fourcc)NV12, width=736, height=576' !

dmaiaccel ! dmaienc_h264 targetbitrate=6000000 bytestream=true copyOutput=false single-nalu=true encodingpreset=2 entropy=0 intraframeinterval=14 idrinterval=10

ratecontrol=2 ! rtph264pay ! udpsink host=199.200.15.61 port=6666 sync=false enable-last-buffer=false

getting reasonable delay and acceptable quality but a small portion of video (approx 80 to 100 pixels) of left side of the image are shown on the right hand side.  image and

video attached for illustration.

 Image may be NSFW.
Clik here to view.

here is the video

(Please visit the site to view this video)

i wrote the video to a file and played the video on vlc but same results,

i am using sdp file with vlc to stream the video on windows pc. 

sdp contents are as under:-

o= IN IP4 199.200.15.61
m=video 6666 RTP/AVP 96
c=IN IP4 199.200.15.61
a=rtpmap:96 H264/90000
a=fmtp:96

also posting my linux bootlogs

Net: Ethernet PHY: GENERIC @ 0x00
DaVinci-EMAC
Hit any key to stop autoboot: 0
reading uEnv.txt

470 bytes read
Importing environment from mmc ...
Running uenvcmd ...
reading uImage

4313408 bytes read
## Booting kernel from Legacy Image at 82000000 ...
Image Name: "RR Linux Kernel"
Created: 2013-08-14 1:19:43 UTC
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 4313344 Bytes = 4.1 MiB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK

Starting kernel ...

Linux version 2.6.32-17-ridgerun (root@sanjay-desktop) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #12 PREEMPT Wed Aug 14 06:48:52 IST 2013
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: DM368 Leopard
Memory policy: ECC disabled, Data cache writeback
DaVinci dm36x_rev1.2 variant 0x8
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 21082
Kernel command line: davinci_enc_mngr.ch0_output=COMPOSITE davinci_enc_mngr.ch0_mode=PAL davinci_display.cont2_bufsize=7188000 vpfe_capture.cont_bufoffset=7188000 vpfe_capture.cont_bufsize=14336000 video=davincifb:osd1=0x0x8:osd0=720x480x16,1350K@0,0:vid0=off:vid1=off console=ttyS0,115200n8 dm365_imp.oper_mode=0 mem=83M root=/dev/mmcblk0p2 rootdelay=1 ip=199.200.15.66 netmask=255.255.255.0 rootfstype=ext3
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 83MB = 83MB total
Memory: 79712KB available (3892K code, 290K data, 128K init, 0K highmem)
SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:245
Console: colour dummy device 80x30
Calibrating delay loop... 222.00 BogoMIPS (lpj=1110016)
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
DaVinci: 8 gpio irqs
NET: Registered protocol family 16
davinci_serial_init:97: failed to get UART2 clock
bio: create slab <bio-0> at 0
DM365 IPIPE initialized in Single Shot mode
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
vpss vpss: dm365_vpss vpss probed
vpss vpss: dm365_vpss vpss probe success
dm365_afew_hw_init
ch0 default output "COMPOSITE", mode "PAL"
VPBE Encoder Initialized
LogicPD encoder initialized
Switching to clocksource timer0_1
musb_hdrc: version 6.0, cppi-dma, host, debug=0
musb_hdrc: USB Host mode controller at fec64000 using DMA, IRQ 12
musb_hdrc musb_hdrc: MUSB HDRC host driver
musb_hdrc musb_hdrc: new USB bus registered, assigned bus number 1
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP reno registered
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
msgmni has been set to 155
alg: No test for stdrng (krng)
io scheduler noop registered
io scheduler anticipatory registered (default)
davincifb davincifb.0: dm_osd0_fb: 720x480x16@0,0 with framebuffer size 1350KB
davincifb davincifb.0: dm_osd1_fb: 0x0x8@0,0 with framebuffer size 810KB
DM365 IPIPEIF probed
imp serializer initialized
davinci_previewer initialized
davinci_resizer initialized
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
serial8250.0: ttyS0 at MMIO 0x1c20000 (irq = 40) is a 16550A
console [ttyS0] enabled
brd: module loaded
loop: module loaded
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron NAND 256MiB 3,3V 8-bit)
davinci_nand davinci_nand.0: controller rev. 2.3
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
usbcore: registered new interface driver usbtest
i2c /dev entries driver
Linux video capture interface: v2.00
vpfe_init
vpfe-capture: vpss clock vpss_master enabled
vpfe-capture vpfe-capture: v4l2 device registered
vpfe-capture vpfe-capture: video device registered
tvp514x 1-005d: tvp514x 1-005d decoder driver registered !!
vpfe-capture vpfe-capture: v4l2 sub device tvp5146 registered
vpfe_register_ccdc_device: DM365 ISIF
DM365 ISIF is registered with vpfe.
af major#: 252, minor# 0
AF Driver initialized
aew major#: 251, minor# 0
AEW Driver initialized
Trying to register davinci display video device.
layer=c40b0c00,layer->video_dev=c40b0d64
Trying to register davinci display video device.
layer=c40b1000,layer->video_dev=c40b1164
davinci_init:DaVinci V4L2 Display Driver V1.0 loaded
watchdog watchdog: heartbeat 60 sec
davinci_mmc davinci_mmc.0: Using DMA, 4-bit mode
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
Advanced Linux Sound Architecture Driver Version 1.0.21.
No device for DAI tlv320aic3x
No device for DAI davinci-i2s
asoc: tlv320aic3x <-> davinci-i2s mapping ok
ALSA device list:
#0: DaVinci DM365 EVM (tlv320aic3x)
TCP cubic registered
NET: Registered protocol family 17
Clocks: disable unused mmcsd1
Clocks: disable unused spi0
Clocks: disable unused spi1
Clocks: disable unused spi2
Clocks: disable unused spi3
Clocks: disable unused spi4
Clocks: disable unused pwm0
Clocks: disable unused pwm1
Clocks: disable unused pwm2
Clocks: disable unused pwm3
Clocks: disable unused timer1
Clocks: disable unused timer3
Clocks: disable unused adc
Clocks: disable unused emac
Clocks: disable unused voice_codec
Clocks: disable unused rto
Clocks: disable unused mjcp
davinci_emac_probe: using random MAC addr: 6e:56:72:65:d2:ad
emac-mii: probed
Waiting 1sec before mounting root device...
mmc0: host does not support reading read-only switch. assuming write-enable.
mmc0: new SDHC card at address e624
mmcblk0: mmc0:e624 SD08G 7.40 GiB
mmcblk0: p1 p2
EXT3-fs warning: mounting fs with errors, running e2fsck is recommended
kjournald starting. Commit interval 5 seconds
EXT3 FS on mmcblk0p2, internal journal
EXT3-fs: recovery complete.
EXT3-fs: mounted filesystem with writeback data mode.
VFS: Mounted root (ext3 filesystem) on device 179:2.
Freeing init memory: 128K
init started: BusyBox v1.18.2 (2013-07-12 09:28:32 IST)
starting pid 984, tty '': '/etc/rcS'
Starting System
done.
Welcome to
__________ .__ .___ __________
\______ \|__| __| _/ ____ ____ \______ \ __ __ ____
| _/| | / __ | / ___\ _/ __ \ | _/| | \ / \
| | \| |/ /_/ | / /_/ >\ ___/ | | \| | /| | \
|____|_ /|__|\____ | \___ / \___ >|____|_ /|____/ |___| /
\/ \//_____/ \/ \/ \/

Embedded Linux Solutions

For further information see:
http://www.ridgerun.com
Build host: sanjay-desktop
Built by: root
Build date: Wed, 14 Aug 2013 06:49:43 +0530
Build tag: leopard
Configuring network interfaces
Error while running '/etc/rc.d/S30network'.
Starting D-Bus message bus system
Starting Ipipe daemon
Loading coprocessors modules...
Loading cmem from 0x86786e20 to 0x87786e20
CMEMK module: built on Jul 12 2013 at 09:39:45
Reference Linux version 2.6.32
File /home/sanjay/work/t.dm36xEvalSdk/proprietary/dvsdk-4_02_00_06/dvsdk/linuxutils_2_26_01_02/packages/ti/sdo/linuxutils/cmem/src/module/cmemk.c
allocated heap buffer 0xca000000 of size 0x1000000
heap fallback enabled - will try heap if pool buffer is not available
CMEM Range Overlaps Kernel Physical - allowing overlap
CMEM phys_start (0x1000) overlaps kernel (0x80000000 -> 0x85300000)
cmemk initialized
EDMAK module: built on Jul 12 2013 at 09:39:48
Reference Linux version 2.6.32
File /home/sanjay/work/t.dm36xEvalSdk/proprietary/dvsdk-4_02_00_06/dvsdk/linuxutils_2_26_01_02/packages/ti/sdo/linuxutils/edma/src/module/edmak.c
IRQK module: built on Jul 12 2013 at 09:39:47
Reference Linux version 2.6.32
File /home/sanjay/work/t.dm36xEvalSdk/proprietary/dvsdk-4_02_00_06/dvsdk/linuxutils_2_26_01_02/packages/ti/sdo/linuxutils/irq/src/module/irqk.c
irqk initialized
Starting Dropbear SSH server: dropbear.
Starting GStreamer Daemon

Please press Enter to activate this console.

i  doubt some setting issue with v4l2src or may be caps but not able to figure out, any help will be appreciated.

Asad 

Part Number:SN74AHC8541

Hi Team,

I have a question at SN74AHC8541.

Is there a protection circuit in Y pin? For example, ESD protection circuit.
If there is a protection circuit, is it VDD or GND? Or both?
If the Ypin is broken, is it open or short?

Best Regards,
Ishiwata

Part Number:BQ28Z610EVM-532

Hi,

I would like to ask what is the default baud rate of the BQ28Z610EVM-532. I have an MCU with Fast Mode I2C running in 400KHz. The MCU has 2 I2C Slaves, one is a custom I2C Slave and the other is the BQ28Z610EVM-532. The MCU was able to detect the custom I2C slave but it was not able to detect the BQ28Z610EVM-532.

I had checked the technical references and the datasheets but i cannot find the baud rate for the BQ28Z610EVM-532.

Thanks,

K

Part Number:DP83822I

Hello,

There seem to be many loopback modes supported in the PHY for MII mode. We are using RMII interface from IMX6 (currently using bare-metal/proprietary OS.). Which loopback modes are supported with RMII please?

Thanks,

Fred

Part Number:TMS320F28030

Tool/software: TI C/C++ Compiler

Hi without optimization the application behaves as designed, with the  optimization set to "4" the firmware misbehaves (misinterpreting SPI packet).

in both cases the micro is in the standalone mode with the debugger not connected.  How does  optimization effects compilation,  suggestion on what is the next course of action.

In anther post it's suggested  it maybe related to constants and .map file, In my case, only after  optimization is invoke does the firmware fail.

thanks 

Part Number:TMS320C6678

Tool/software: TI-RTOS

How to use VLIB_matchTemplate function?

Especially (imgPitch 、tempImgPitch 、scaledTempImgVar 、xDirJump 、yDirJump 、method 、outScorePitch 、outScore 、scratch)

How to define those parameters?

Is there any application example?

Part Number:DLPC3437

I read FPGA status via composer and find FPGA keying(register 6Fh) failed. I checked DLPC3437 software programming guide and there is no description for this. What does FPGA keying failed mean? What I should do to fix this issue? I attached DLPC3437 software programming guide. Thanks.

(Please visit the site to view this file)

Jason

Part Number:TMS320C6655

Tool/software: Code Composer Studio

Hi TI

I'm dealing with some very serious compiler issues and need to look at the generated code using .lst andn .asm files.

It's very hard to read the generated code. Do you know some compile option which provides the comments in the .lst andn .asm files.?

We are using the compile version 7.4.12 and working on switching to version 8.3.3. But there is some issue we need to clarify first

Some thing like this example from one of TI's reference guide:

>>>>>>>>

Example 8-7 SPLOOPW Implementation of C Coded Loop

MVK 8,A0 ;Do 8 loops
[!A0] SPLOOPW 1        ;Check loop
LDW .D1 *A1++,A2       ;Load source value
NOP 1
SUB .S1 A0,1,A0           ;Adjust loop counter
NOP 2                            ;Wait for source to load
MV .L2X A2,B2               ;Position data for write
SPKERNEL 0,0               ;End loop
|| STW .D2 B2,*B0++       ;Store value

End of Example 8-7

<<<<<<<<<<<<<<<<<

Thanks for your help

BR

Tam Tran

Vestas Wind System

Part Number:DP83867CR

Hi,

Could you advise me about compliance test.

When 1000BaseT compliance test is performed using TEST MODE, two item (OUTPUT VOLTAGE) ware fail as follows:
1000 Base-T, Point A Peak Output Voltage(w/ Disturbing Signal)
1000 Base-T, Point B Peak Output Voltage(w/ Disturbing Signal)
They are not enough peak voltages. The point A of actual value of point was 584.1mV and B was 588.4mV. Values of 670mV to 820mV are required to pass the voltage.

There are no particular problems with PHY circuits, power supplies, and settings. I am referring to snla239a.pdf.
Please let me know if there is a way to adjust the peak voltage amplitude.

Regards,
Kenshow

Part Number:CC2531-RF4CE

Hi Experts,

Our customer has been utilizing CC2531 for a remote controller.
They would like to know a Flash update portion in our library.

I am afraid that I am a beginner for RemoTI.
I have downloaded REMOTI-1-4-0 form our http://www.ti.com/tool/REMOTI.

So could you please let me know which API controls the flash update or the related portion?

Best regard,
Hitoshi

Part Number:TPS562209

Hi all,

Customer test the SW pin waveform on several boards and found that one board's switching frequency is higher than normal.

The test conditions are Vin:9.3V; Vout:5V load is no load. Customer want to know 790kHz switch frequency is normal or not.

1. 790kHz

Image may be NSFW.
Clik here to view.

2. normal chip

Image may be NSFW.
Clik here to view.

Part Number:AWR1843

Tool/software: Code Composer Studio

in this version,the hwa used to do 1d and 2d fft.

at the 2d fft, two EDMA used to transfer data from L3 to hwa local memory 0 and 1.

and the other two EDMA used to transfer data from hwa local memory 2 and 3 to detmatrix.

all the EDMA used the shadow_link and chain. 

I try to modify the source address or dest address of the EDMA.

but the code is error:[c674x]{module#34}: line 215 :error {id : 0x10000,args:[0x81ea3d,0x81ea3c]}

is the source address or dest address of the EDMA fixed？

and in the one hot signature,how does the one hot shadow link works?

does the one hot shadow link has a relationship with the source or dest address of the EDMA?

Thank you!

Part Number:TMS320C6746

Tool/software: Code Composer Studio

Hi,

I am using TMS320C6746 custom board. I have configured all my timers to generate interrupts.

Timer0--> 125us timer

Timer1-->WatchdogTimer 10ms(No specific interrupt is mapped to it but watchdog is enabled)

Timer2->1ms Timer(this timer starts inside 125us timer)

Timer3--> Two 32 bit timers, lower 32 bit timer is 10ms timer and higher 32 bit timer is 100ms timer

Timer2 has higher priority followed by Timer0, Timer3 lower and Timer3 higher. In my main function I start Timer0 and Timer3 and enter a while(1) loop in which some code is written. 

When I debug my code , I'm entering into while(1) only for the first time and only the code in ISR corresponding to Timer0 interrupt is getting executed and i'm unable to get back to while(1) loop in main() even I put a break point inside while(1) loop(no break statement inside while(1) loop). I'm clearing the IFR corresponding to Timer0 interrupt upon entering Timer0 ISR and enabling only those interrupts which are having higher priority than Timer0 interrupt to pre-empt  and enabling all the interrupts just before exiting the ISR. Now. although the IFR's corresponding to Timer3 timers were raised I'm unable to enter the corresponding ISR's  by putting a break point inside them. When I allow other interrupts to pre-empt the timer0 interrupt by enabling them just after entering timer0's ISR , I am able to enter into other interrupts ISR's but not able to enter into while(1) loop in main(). I don't have any Idea why this is happening. Can someone please help me out. (.far section is in SDRAM and .bss in L2(I'm not sure whether this has anything to do with my problem) ). The CCS version i'm using is v7.3.(The code is not getting stuck in any of the loops in ISR corresponding to Timer0).

Regards,

Vishnu.

Part Number:MSP-TS430RHB32A

Dear all

I'm sending a file which includes our measurement results, the configurations and our source code.

According to the results, ADC seems to output current. What kind of causes can you think of?

(Please visit the site to view this file)

A: When we connect A1.0+ and GND by a resistor, the value of ADC changes depending on the resistor value.

B:When we connect A1.0+ and GND , and between A 1.0- and GND by each a resistor,

the difference of ADC value when we use resistors or just short seems to be in proportion to Vin.

Even when measuring the ADC input with an external measuring instrument,

there was a difference in voltage value depending on the presence or absence of resistance.

I guess it is due to the leakage current of the protection diode, what do you think?

We'd like to use this chip for our development though, our customer says until we figure out the reason clearly, they can't use this for their mass production.

Best regard,

Megumi Nishi

Part Number:TIDA-01292

Hi Team,

This is with reference to the inverter design reference file of TIDA-01292. The gate driver part number is LM5101BMA & the input PWM signal to gate driver is from TMS320F28027 LaunchPad. 

The input threshold voltage level of LM5101B is 4.5V(min) to 6.3V(max) . The launchpad VCC is 3.3V, then how your are meeting the requirement of threshold voltage for input signals of gate driver? 

Are you using any buffer/level shifter on LaunchPad to convert 3.3V PWM signal to 6.3V level? 

Image may be NSFW.
Clik here to view.

Thanks,

Vaibhav

Part Number:CC2652R

Tool/software: TI-RTOS

Hello Friends

I am new to CC2652r dev kit and simplelink_cc13x2_26x2_sdk_3_10_01_11

I am going to use IO pin 24(Analog or Digital) as analog input

Can anyone tell me how to config that pin for my purpose.

Sample code on simplelink_cc13x2_26x2_sdk_3_10_01_11 SDK will be good for me.

Thanks in advance