Part Number:UCC27714
Why are there no graphs or plots of the HO/LO output drive current relative to PWM frequency and +/- IGPK capability shown in data sheet, am I expecting to much useful information?
Am I simply spoiled by other data sheets that express output drive current capability showing curves across various temperature ranges as a given way of relating IC current and power dissipation restraints.
Given that in an inverter MOSFET IAS collapse only characterize a recovery event after some kind of catastrophic circuit fault caused IAS to occur in the first place (as gate drive current is being applied / misapplied), how can lower or even higher gate drive current reduce or arrest the event entirely? Is not that a selling point to upgrade a typical lower current gate driver to higher gate drive current?
How can anyone be sure any expected HO/LO drive current at various HI/LI PWM frequency, when only being elaborated in AMR as a maximum 100ns PW guessing that infers 10Mhz? Are we supposed to guess what the current will be at various HO/LO PW or trust noting will go wrong if the HI/LI PW fall below 100ns but never no less than 10us if the HO/LO is suddenly shorted to ground. How can that be proper way to express HO/LO drive current capability of any PWM device so that it makes logical sense without actually developing a drive circuit and testing UCC27714 at various HI/LI PWM frequency?
Reminds me of the cartoon, roadrunner chased by coyote strapped to a rocket, even from a well though out schematic the coyote always crashed anyway.