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DM385: Strange Boot ROM behaviour

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Part Number:DM385

Hi!

We have two generations of board with DM385 cpu. The boards are pretty the same in the terms of cpu/power/memory schematics.

We observing strange boot behaviour on new boards(it works ok on old boards).

During board bringup we are trying to boot from SD card. 

U-Boot(SPL) starting ang hangs. First we thought this is due to wrong clock settings. But after we'd enabled debug printouts in SPL we see that SPL can't read u-boot image from SD card because of internal error.

Further investingating showed that when FAT device is registered in spl_register_fat_device variable fat_registered contains thrash value.

This variable is defined as:

static int fat_registered;


It is static and should be set to zero during load process.

When we take exactly that binary and run it on old board everything going fine and fat_registered variable contains zero as expected.

We found that on our new board we have cpu with part number: DM385AAARD21F and on our old boards DM385AAAR11.

Boot ROM of both boards are the same(same version and same content).

This looks very strange. This is SPL, running in L1, no DDR in use...

Can somebody help with this? 


TMP275: EVMs to try out temp sensors?

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Part Number:TMP275

Hi,

I'm looking for potential EVMs which i can use for mounting TMP275 as i'm trying to communicate with the temp sensor via I2C bus. Please advise. Thanks.

Regards,

Leo

ADS1298: Input Common Mode Range

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Part Number:ADS1298

Along those same lines, I don't understand the input common-mode range equation.  

Why is the gain in the formula if it's the input common mode? 

Thank you. 

- Colleen 

IWR6843ISK: "Mirror"/image signal peak in data acquired in mmWave Studio

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Part Number:IWR6843ISK

Dear experts,

I see a strong mirror/image signal peak in my measurements, which appears at (Maximal Distance - Distance of Fundamental Signal Peak). 

Moving a corner reflector away from the radar results in a similar offset of the image peak with respect to the maximal distance.  I tried several configurations and number of points but the parasitic peak is still there.

Presumably this is caused by a disbalance between the I and Q signals when their phase difference differs from 90 degrees at the signal frequency. 

I also tested an ISK-ODS board for the same configuration, and the image peak is still there. This halfs the operational distance unfortunately... I didn't see it in the IWR1443 by the way. 

The data was acquired in Complex1 format. In Complex2 the image appears as a peak at a negative distance simmetrically wrt 0. 

Any suggestions?  Thank you in advance.

Best regards,

Timofey

IWR6843ISK:  512 points, corner reflector at 1.1 m

1024 points:

Corner reflector at 1.7 m:

Corner reflector at 2.6 m:

TMS320F28069: QEPSTS.FIMF (First index marker flag) not working as expected

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Part Number:TMS320F28069

The FIMF flag, once set by index pulse, then cleared by software request (by writing a 1 to the field), does not trigger again until after a full device reset (power down in our case).

Please see the related post.

Can someone confirm this issue also occurs on the TMS320F28069(F/M)? I seem to have this issue, but cannot find it documented in the Errata.

Also, is there a workaround on this MCU, like the DevCfgRegs.SOFTPRES4.bit.EQEP1 suggested in another post?

Best regards,

Rob.

LMZ30604: Can this be a good replacement for EN6347QI 4A Power SoC?

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Part Number:LMZ30604

Hi,

I would like to verify if LMZ30604 would be a good part to replace EN6347QI which is a 4A Power SoC? Are there anything we need to take note of with regards to this recommendation? Please advise.

Regards,

Leo

LP339-N: Alternative Part?

ONET1151L: CML Output Current

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Part Number:ONET1151L

Hi,

I'm trying to understand the 85mA p-p MODulation current spec, coming up with two questions:

1.)  Is the 85mApp MODulation current spec referring to that deliverable to an external (10-Ohm) load, or, referring to the internal diff pair sink itself ?

If the spec refers to the internal sink, it seems only half of the current (42.5mA) is available at the load.

2.)  What is the voltage compliance at the MOD pin?

Thanks for your help


LAUNCHXL-CC2650: CC2650 BLE Power consumption

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Part Number:LAUNCHXL-CC2650

Hello!

I want to research power consumption BLE Radio Module.

First, I connected a ammeter and a voltmeter between the voltage source and the board CC2650 LauchPad (the circuit below is in the picture), but the ammeter shows the total current consumed by the board, and not just the radio module. 

Are there pins on the CC2650 Lauchpad, which allow to measure the current consumed by the radio module BLE. Or how else can this be done?

TVS3300: TVS behavior for voltage clamp pulse with a duration up to 0.1 sec

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Part Number:TVS3300

Good day Colleagues,

Could you tell me, did we test the TVS diodes for voltage clamp response with pulses of 0.1 sec duration?

I see the datasheet is indicating 30us pulse.

My customer would like to see behavior of voltage clamp up to 0.1sec.

Is it possible to make these tests?

Thank you, Mikhail

TAS5162: THD specs

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Part Number:TAS5162

Hi,
In our tests we are having difficulty to achieve the THD levels given in the datasheet. - can you please provide some more detailed description how TAS5162 THD measurements were carried out, especially what test signal was used ?  In digital class D typically to get pure THD figures for the TAS stage the PWM test signal would have to be specfically conditioned.

Would it be possible to get THD measurements with individual harmonics values shown ? - that would also help us much to better analyze the THD in our appliaction.

Regards, Pawel

BQ27Z561EVM-011: Time consuming problem of learning cycle procedure.

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Part Number:BQ27Z561EVM-011

Hello,

I am a newbie in battery gauge domain. I need to perform a learning cycle on a NCR18650 Lithium Ion battery by BQ27Z561EVM-011 battery gauge and BQ27GDK000EVM kit. I have already done the current and voltage calibration and uploaded the ChemID.

Now I meet a problem that the learning procedure takes too much time in my case. According to the video guide for learning cycle (https://training.ti.com/how-perform-successful-learning-cycle-gauges?keyMatch=LEARNING%20CYCLE%20VIDEO&tisearch=Search-EN-Everything), in order to accomplish a successful learning cycle, the following steps should be performed:

Step 1). Discharge battery by C/5 rate (in theory it takes 5 hrs);

Step 2). Relax battery for a period of time (according to the guide https://e2e.ti.com/blogs_/archives/b/fullycharged/archive/2016/03/02/how-to-run-a-learning-cycle, it should take at least 5 hrs);

Step 3). Charge the battery by C/2 rate (by the data sheet of NCR18650B, it should take around 4 hrs);

Step 4). Relax battery for a period of time (according to the guide https://e2e.ti.com/blogs_/archives/b/fullycharged/archive/2016/03/02/how-to-run-a-learning-cycle, it should take at least 2 hrs);

Step 5). Discharge battery by C/5 rate (in theory it takes 5 hrs).

Step 6). Relax battery for a period of time (according to the guide https://e2e.ti.com/blogs_/archives/b/fullycharged/archive/2016/03/02/how-to-run-a-learning-cycle, it should take at least 5 hrs).

If the procedure above is correct, the total time of a full learning cycle should be 5 + 5 + 4 + 2 + 5 + 5 = 26 hrs.

In the post https://e2e.ti.com/support/power-management/f/196/t/461819?AutoCycle-BQStudio, it reads that "the Auto cycle feature is not supported using the EV2400". Since I am currently using the on-board EV2400 of BQ27Z561EVM-011, the only choice for me is to perform the learning cycle manually. While normally,  no one can keep monitoring the learning cycle for 26 hrs. By this reason, I come out several solutions for my case:

Solution 1). Decrease the time cost of each step listed above, like discharge by a higher rate, for example C/2 and let the battery relax less time, e.g. 2 hours for each step of relaxing. I know this solution looks crazy and probably not feasible. I still want to ensure if increasing discharge rate and decreasing relax time is feasible for the learning cycle. Let's call it Question 1).

Solution 2). Increase the relax time of some relax step in order to separate the procedure into several days, for example:

Day1: Discharge battery by C/5; relax until next morning;

Day2: Charge the battery by C/2; relax until next morning;

Day3: Discharge battery by C/5; relax until next morning.

By this approach, the problem could be solved. While I still have some questions (following previous index):

Question 2): Will the result of learning cycle be inflicted by increasing the relax time?

Question 3). Can I turn off battery gauge and/or GDK during relaxing time?

Thanks for your patience to read my question.

Waiting for your reply sincerely,

Wenlong

CSD86360Q5D: PSPICE model

TMS320C6711D: The DSP is locking up =.

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Part Number:TMS320C6711D

We are using a TMS320C6711DZDP200 in our design..

Our CLKIN has a 150MHz clock input...After continuous operation for an hour or two the System Locks up. We have isolated it down to the DSP and possibly the 150MHz clock input. We do not have a WDT in the design..Our ECLKIN signal is 100MHz.. our ECLKOUT is 100MHz... What I cannot tell is if it is the DSP how can I prove it.. My series terminated resistor is 240 ohms.. My 150MHz is coming from an Altera MAX 10 FPGA.. The 240 is high... The Lockups only occur on a few of our boards.. Any suggestions?

[FAQ] CCS: Project build error: error: xdc.cfg.SourceDir : Build of generated source libraries failed: exit status = 2:

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Tool/software: Code Composer Studio

When building a TI-RTOS based CCS project it fails with the following error:

error: xdc.cfg.SourceDir : Build of generated source libraries failed: exit status = 2:

What is the reason for the error?


TMS320C6657: RESETFULL not functioning the same as a power cycle

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Part Number:TMS320C6657

Hi

We are experiencing an issue where the DSP does not appear to initialise properly (possibly cache issues) after RESETFULL.

It is our understanding that a RESETFULL should be functionally equivalent to a power cycle of the device but this does not seem to be the case everytime. In a previous thread there was mention of the software running having some effect on the behaviour of RESETFULL but that thread went dead.

Our reset pulsewidth is 150mS and the reset stat timing appears to be correct.

Any help would be appreciated.

Thanks

Dhar

TPS23880: SRAM Programming I2C issues

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Part Number:TPS23880

I am having difficulties programming the SRAM on the TPS23880 device on my embedded board. It appears that the ACK from the 23880 gets missed periodically. (Usually about 2/3 of the way through programming the main SRAM code). Looking at the signal on the scope, it appears that the master I2C clock is ok, but the ACK doesn't appear. From the perspective of my firmware, the I2C driver stalls (times out) and needs to be reset. At the moment, I am not able to resolve whether this is a hardware issue (my pullup resistors are wrong), a driver issue (the clocking is quite right in my firmware) or something isn't quite right in the 23880.

This issue is easily detectable in my firmware's state machine for programming the SRAM. Consequently, if I could successfully restart the I2C programming sequence from the middle, I could recover and complete the process. Is there any way that I could back up to an address that I know I have successfully written, reset the beginning address and continue programming from that point? Also, can the SRAM be programmed by sending blocks of data bytes, or does it have to be programmed one byte at a time?

Any hints as to how to identify the root cause of my problem would also be greatly appreciated. Also, workarounds that get me up and running in the short run would helpful.

LME49726: LME49726

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Part Number:LME49726

Need to confirm setup for 5 volt single supply low gain value non inverting. Please comment on our approach and if it is correct and not what we need to do. Thank you. 

TMP513: Measuring voltage limit value

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Part Number:TMP513

Hi everyone! My problem is i cannot understand, what value i need to write in , for exapmle, bus voltage positive register. I cannot find this information in datasheet and forum. According datasheet, for 32v value corresponds hexidemical value 1f40 and decimal 8000, so what value must corresponds for 17.5 v? I need some algorithm how can i convert this value to data to write into register. I've see an example in datasheet, how can i convert value in shunt voltage register, but that algorithm didnot work with other.

Sorry for my bad english!

DS90UB948-Q1: DS90UH948 + DS90UB921

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