↧
TINA/Spice/AM26C31: TINA SPICE model for the AM26C31
↧
OPA211: the difference of OPA211AIDGKR and OPA211IDGKR
Part Number:OPA211
Dear parter,
can you tell me the difference between OPA211AIDGKR and OPA211IDGKR? thanks.
↧
↧
TPS65917-Q1: difference between O917A134 & O917A148
Part Number:TPS65917-Q1
Hi TI pals
The orderable device description of TPS65917 device marking mentions about different OTP,
O917A148TRGZRQ1 is designed with J6 SoC DRA716, and O917A134TRGZRQ1 is deigned with DRA725
in our project for HARMAN LGA module. Because these two part number both are TPS65917-Q1.
Could O917A148TRGZRQ1 substitute for O917A134TRGZRQ1?
↧
PMP20345: Dimmable Exit Light Design
Part Number:PMP20345
Hi,
One of my customer wants to work on a new Dimmable Exit Light Design. They are driving a string of LED at constant current.
The requirement as follow:
Input: AC 230V
Output: 48V 180mA and 360mA (2 designs)
I checked and found this reference design (PMP20345), which is quite close to the requirement, except dimming control.
Is there an easy way to add in dimming control to this reference design ?
Or is there any other better solution to achieve the above requirement ?
Thanks and Regards,
CM.
↧
CC2640R2F-Q1: Timing requirement of rising pin - VDDR/VDDR_RF/VDDS/VDDS2/VDDS3/VDDS_DCDC/...
Part Number:CC2640R2F-Q1
Team,
My customer who employs the CC2640R2F-Q1 would like to know the timing requirement of rising pin - VDDR/VDDR_RF/VDDS/VDDS2/VDDS3/VDDS_DCDC/...
The VDDx pins on their board would connect with difference decoupling cap each other. So the rising time of each are a bit difference during power-up. I glanced over the data sheet. It tells that we define only skew rate. Do we have strict rule when power-up sequence for the VDDx pins?
Regards,
Nonaka
Team,
My customer who employs the CC2640R2F-Q1 would like to know the timing requirement of rising pin - VDDR/VDDR_RF/VDDS/VDDS2/VDDS3/VDDS_DCDC/...
The VDDx pins on their board would connect with difference decoupling cap each other. So the rising time of each are a bit difference during power-up. I glanced over the data sheet. It tells that we define only skew rate. Do we have strict rule when power-up sequence for the VDDx pins?
Regards,
Nonaka
↧
↧
DAC161S997: Doubts in the 4 to 20 mA current loop transmitter reference design - TIDUAM6
Part Number:DAC161S997
Hi Team.
Please address the following questions:-
1. I referred "4-20 mA current loop transmitter reference design - TIDUAM6". Refer page 16,17/27 of the document. Equation 6 in the description below says Iout = Iin + Ir21 + Ir22 whereas I believe it has to be Iout = Iin = Ir21 + Ir22. Please do explain if something is wrong at my end.
2. Can you please elaborate me the description below figure 12 of the document. How 2.5 V came out as a reference value and why not some other value ?
Regards.
↧
CD74HC4050: Is the effective input voltage range dependent on Vcc?
Part Number:CD74HC4050
Hello.
I am looking for an IC that can down convert a 12V or 5V signal to 3.3V. Is CD74HC4050 possible?
I am worried whether problems will arise if VI becomes higher than VCC.
(Operating Conditions are written as Vi ... 0 V to 15 V.)
Is the effective input voltage range dependent on Vcc?
↧
Linux/DP83869HM: DP83869HM LINUX DRIVER
↧
AM3352: Whether AM3352 supports The PCM4201 outputs 24-bit linear PCM audio data
Part Number:AM3352
Hello sir,
We have plan to use AM3352 with PCM4201 ADC in Audio Encoder project.
The PCM4201 outputs has 24-bit linear PCM audio data.
Whether MCASP interface of AM3352 support 24-Bit Linear PCM Output Data format of PCM4201 ADC ?
If above condition is possible, then how to connect PCM4201 ADC pins ( DATA, FSYNC, BCK, SCKI ) with AM3352 ?
Regards
Lakshmanan V
↧
↧
LM5165: LM5165-Y used as adjustable using "extra" voltage divider in feedback
Part Number:LM5165
Hi everyone,
We have a dessign where we need to use the adjustable version of the LM5165 (we need a 12V output). However for prototyping we are not able to solder manually the VSON-10 package so we are trying to use the LM5165-Y (3.3V fixed version) with the VSSOP package, setting an external "extra" voltage divider plus the internal one in order to make the output voltage higher.
For the moment we are not able to get more than 10.53V in the output, no matter which external resistors we add on the feedback. Also we see a kind of instability,(the output is not fixed in all the input range we need : 17-40V.
Is it possible what we are trying? Is there any internal limitations? We are using the LM5165 in PFM mode (RT to GND), no hysteresis (enable always to VIN), CCS=27nF and current limit set to the minimum (60mA), we need only 12V/30mA.
Best regards
↧
RTOS/CC1310: Packet format and parameters related issues
Part Number:CC1310
Tool/software: TI-RTOS
Hi Team，
When I read the proprietary RF section of the reference manual, I encountered a lot of problems that I could not understand.First, RF_cmdPropTx->pktConf.bVarLen = 0x1, which means the length is sent as the first byte. However, the length field information is not reflected in the rfPacketTx example.
/* Create packet with incrementing sequence number and random payload
packet[0] = (uint8_t)(seqNumber >> 8);
packet[1] = (uint8_t)(seqNumber++);
uint8_t i;
for (i = 2; i < PAYLOAD_LENGTH; i++)
{
packet[i] = rand();
}There is no bVarLen parameter in the CMD_PROP_TX_ADV command, but the length byte must be filled in the WOR-TX example.
memcpy(RF_cmdPropTxAdv, RF_cmdPropTx, RADIO_OP_HEADER_SIZE);
packet[0] = PAYLOAD_LENGTH;
packet[1] = (uint8_t)(seqNumber >> 8);
packet[2] = (uint8_t)(seqNumber++);
uint8_t i;
for (i = 3; i < PAYLOAD_LENGTH +1; i++)
{
packet[i] = rand();
}Can you explain why?
↧
ADS1672: Delay of DRDY of ADS1672
Part Number:ADS1672
Dear, All
Customers are using the ADS1672.
Multiple ADS1672 are used but simultaneous sampling is necessary.
For this reason, I have the following questions.
Furthermore, they use the mode of "SCLK_SEL = 1".
a. Under the following conditions, can each ADS1672 be guaranteed to sample on the same CLK edge?
- Connect the same CLK to the CLK terminal of each ADS1672.
- Enter the START signal by observing the specified value of "Figure 3. START Timing".
b. They want to know the CLK edge that output DRDY to see if the ADS1672 was sampled on the same CLK edge.
Therefore, I want to know the Max value of the DELAY value from CLK to DRDY.
Please tell me the Max value of Tclkdr. If it can not be guaranteed, the assumed value (design value etc) is also good.
The questions in b. are necessary to determine the maximum frequency of the CLK they can use.
Please tell me these two.
Thanks, Masami M.
↧
TPS2419: Suggested MOS
↧
↧
TMS320C6654: Heatsink fastener load force
Part Number:TMS320C6654
Hi,
The customer is now designing a heat sink for C6657. Could you tell us what the maximum pressure (load force) of this device is ?
I found the similar question about AM5728 below. How about C6657 ?
Thanks and regards,
Hideaki
↧
CC3220MOD: Socket error during OTA update
Part Number:CC3220MOD
Hey community,
During the OTA update process, the following error shows up, which makes the update fails. Any idea what's the cause of it ?
"Error accepting client connection, error -95"
Error -95 : "Operation not supported on transport endpoint" (SL_ERROR_BSD_EOPNOTSUPP).
Thanks in advance !
↧
LCL filter calculation implemented in Microsolar inverter.
hai,
i happen to see the reference design of a Grid tie based micro solar inverter from ti.
can you please share me the design document ,or how calculations were done to implement the LCL filter design in the grid tie section.Is this the way to implement the Grid Tie? How were the values of Li,Lg and Cf calculated?How was the value of L11 calculated in the design.Actually do we need that?am asking this because i couldn't find the induct or either calculated or implemented in TI Grid connected reference design:
www.ti.com/.../tievm-hv-1ph-dcac
Actually which is the correct way of implementing LCL?i have attached the screen shot of both reference designs:
Please hep me with this doubts.Since my project is in a critical stage, fast response is expected.
↧
CCS/DLPNIRNANOEVM: Errors while compiling: cannot open source file "ti/sysbios/family/arm/m3/Hwi.h": Invalid argument
Part Number:DLPNIRNANOEVM
Tool/software: Code Composer Studio
Hello,
I hope I'm writing in the right forum.
I have the DLP NIRscanNano EVM and want to compile the latest code in the first steps. I created the Workbench as described in the latest NIRscanNano manual (DLPU030G, Appendix A to C.1.3).
Now that I want to compile the main Tiva source (Appendix C.2), I received the following error message:
Description Resource Path Location Type cannot open source file "ti/sysbios/family/arm/m3/Hwi.h": Invalid argument .ccsproject /Mobile Spectroscopy TIVA EVM line 15, external location: C:\ti\tirtos_tivac_2_10_01_38\products\bios_6_41_00_26\packages\ti\sysbios\family\arm\m3\package\internal\Hwi.xdc.h C/C++ Problem gmake: *** [../src/sysbios/sysbios.aem4f] Error 2 Mobile Spectroscopy TIVA EVM C/C++ Problem gmake: Target 'all' not remade because of errors. Mobile Spectroscopy TIVA EVM C/C++ Problem gmake[1]: *** [BIOS.obj] Error 258 Mobile Spectroscopy TIVA EVM C/C++ Problem gmake[1]: *** [m3_Hwi_asm.obj] Error 1 Mobile Spectroscopy TIVA EVM C/C++ Problem gmake[1]: Target 'all' not remade because of errors. Mobile Spectroscopy TIVA EVM C/C++ Problem
Hope someone can help me with my problem.
Best regards
Michael
↧
↧
TMS320F280049C: TMS320F280049C Boot ROM CRC
Part Number:TMS320F280049C
Hello all,
I was reading document SPRUFN6–December 2008 (link provided at the end), regarding Boot Rom for F2802x devices. I was wondering if there is a similar one for TMS320F280049C. I am trying to identify Boot ROM CRC and revision values so it can be checked during application start up, it is a request from customer. Could you kindly help me out with this...
Thanks in advance for the time and best regards,
Alberto Peyro
link to file: 
↧
TPS2051C: Is there a device of FLT active "H" like TPS2051C
↧
CCS/CC1352R: CC1352R
Part Number:CC1352R
Tool/software: Code Composer Studio
Hi All,
I am working with TI 15.4 stack sensor example in NON_BEACON_MODE. But I want to work with sensor example code in FH_mode .so, I have enbaled CONFIG_FH_ENABLE as TRUE(by default it is false).
I want to know to work with FH_MODE do I need to make any other changes in sensor example code.
Thanks&Regards
NIHARIKA R.V
↧