Part Number:TMS320F28377D
Tool/software: Code Composer Studio
Hi.
I develop a program, for a long time, that are locate on CPU1, CPU1_CLA, CPU2 and CPU2_CLA.
Recently, linker told me to extend program space for CPU2 (.text section in cmd file) and I execute this task as I did before for CPU1. For clarity, I attach the cmd file with previous comment statement modified:
// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000080, length = 0x000380
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
// RAMLS4 : origin = 0x00A000, length = 0x000800
// RAMLS5 : origin = 0x00A800, length = 0x000800
// RAMGS0 : origin = 0x00C000, length = 0x001000
// RAMGS1 : origin = 0x00D000, length = 0x001000
// RAMGS2 : origin = 0x00E000, length = 0x001000
// RAMGS3 : origin = 0x00F000, length = 0x001000
// RAMGS4 : origin = 0x010000, length = 0x001000
// RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS0_TO_5 : origin = 0x00C000, length = 0x006000
// RAMGS6 : origin = 0x012000, length = 0x001000
// RAMGS7 : origin = 0x013000, length = 0x001000
// RAMGS8 : origin = 0x014000, length = 0x001000
// RAMGS9 : origin = 0x015000, length = 0x001000
// RAMGS10 : origin = 0x016000, length = 0x001000
// RAMGS11 : origin = 0x017000, length = 0x001000
// RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS14_STRUCT : origin = 0x01A000, length = 0x000800
RAMGS14_ADC_EXT : origin = 0x01A800, length = 0x000800
RAMGS15_STRUCT : origin = 0x01B000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800
// RAMLS0 : origin = 0x008000, length = 0x000800
// RAMLS1 : origin = 0x008800, length = 0x000800
// RAMLS2 : origin = 0x009000, length = 0x000800
// RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
// RAMGS6 : origin = 0x012000, length = 0x001000
// RAMGS7 : origin = 0x013000, length = 0x001000
// RAMGS8 : origin = 0x014000, length = 0x001000
// RAMGS9 : origin = 0x015000, length = 0x001000
// RAMGS10 : origin = 0x016000, length = 0x001000
// RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS6_TO_11 : origin = 0x012000, length = 0x006000
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
// .text : >> RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3/* | RAMLS4*/, PAGE = 0
.text : >> RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMGS0_TO_5, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.stack : > RAMM1, PAGE = 1
.ebss : > RAMLS5, PAGE = 1
.econst : > RAMLS5, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1
/* CLA specific sections */
Cla1Prog : > RAMLS4, PAGE = 1
// CLADataLS4 : > RAMLS4, PAGE = 1
CLADataLS5 : > RAMLS5, PAGE = 1
CLA1mathTables : > RAMLS5, PAGE = 1 // Section Added at 04/2017
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
// SHARERAMGS0 : > RAMGS0, PAGE = 1
// SHARERAMGS1 : > RAMGS1, PAGE = 1
// SHARERAMGS2 : > RAMGS2, PAGE = 1
// SHARERAMGS3 : > RAMGS3, PAGE = 1
// SHARERAMGS4 : > RAMGS4, PAGE = 1
// SHARERAMGS5 : > RAMGS5, PAGE = 1
// SHARERAMGS6 : > RAMGS6, PAGE = 1
// SHARERAMGS7 : > RAMGS7, PAGE = 1
// SHARERAMGS8 : > RAMGS8, PAGE = 1
// SHARERAMGS9 : > RAMGS9, PAGE = 1
// SHARERAMGS10 : > RAMGS10, PAGE = 1
// SHARERAMGS11 : > RAMGS11, PAGE = 1
// SHARERAMGS12 : > RAMGS12, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// SHARERAMGS13 : > RAMGS13, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// SHARERAMGS14 : > RAMGS14, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
SHARERAMGS14_STR : > RAMGS14_STRUCT, PAGE = 0
SHARERAMGS14_ADC : > RAMGS14_ADC_EXT, PAGE = 0
SHARERAMGS15_STR : > RAMGS15_STRUCT, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} > RAMM0, PAGE = 0
#else
ramfuncs : > RAMM0 PAGE = 0
#endif
#endif
#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS5, PAGE = 1
.scratchpad : > RAMLS5, PAGE = 1
.bss_cla : > RAMLS5, PAGE = 1
.const_cla : > RAMLS5, PAGE = 1
#endif //CLA_C
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Naturally, Linker stopped to show me error about lack program space but when I try to loading code with my debug session, following observations need to be made:
1) CPU1 code is loaded correctly and, at the end of total programming process, the debugger point to main address;
2) CPU1_CLA code is loaded correctly and starting when I lunch CPU1 code to generate a sw trigger for various task;
3) CPU2 code seems to be loaded correctly...
2) CPU2_CLA code is loaded correctly and waiting a sw trigger from CPU2 code.
After program stage are completed, console show me follow:
C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU2: GEL Output:
Memory Map Initialization Complete
C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
If I select Debug Tab I see that:
![]()
Differently than usual, CPU2 code start to run immediately... If I suspend it, console show me the follow error even if I don't insert any breakpoint:
C28xx_CPU2: Trouble Removing Breakpoint with the Action "Finish Auto Run" at 0x9800: (Error -1066 @ 0x9800) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 8.0.903.4)
Finally, when I return in Debug Tab, I see CPU2 suspended where PC point to 0x3FE00A address where no symbol are defined. I obtain the same behavior if I load again code by load command (CPU2 running immediately and ...). I know, if I not in error, that address is a BOOT ITRAP; unfortunately, I don't understand where I stuck my cmd linker file. I tried to take a look at my map file but I didn't find nothing strange (obviously I attach that follow).
Can someone help me to understand what's going on? Thank's a lot.
Diego
******************************************************************************
TMS320C2000 Linker PC v18.1.1
******************************************************************************
>> Linked Wed Feb 20 14:19:17 2019
OUTPUT FILE NAME: <PD1801FW002V01_CPU2-UPS_LC.out>
ENTRY POINT SYMBOL: "code_start" address: 00000000
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
BEGIN 00000000 00000002 00000002 00000000 RWIX
RAMM0 00000080 00000380 00000243 0000013d RWIX
RAMLS0 00008000 00000800 00000800 00000000 RWIX
RAMLS1 00008800 00000800 00000800 00000000 RWIX
RAMLS2 00009000 00000800 00000800 00000000 RWIX
RAMLS3 00009800 00000800 000007fd 00000003 RWIX
RAMD0 0000b000 00000800 00000800 00000000 RWIX
RAMGS0_TO_5 0000c000 00006000 00000029 00005fd7 RWIX
RAMGS14_STRUCT 0001a000 00000800 00000022 000007de RWIX
RAMGS14_ADC_EXT 0001a800 00000800 00000020 000007e0 RWIX
RAMGS15_STRUCT 0001b000 00001000 0000002c 00000fd4 RWIX
RESET 003fffc0 00000002 00000000 00000002 RWIX
PAGE 1:
BOOT_RSVD 00000002 0000007e 00000000 0000007e RWIX
RAMM1 00000400 00000400 00000100 00000300 RWIX
ADCA_RESULT 00000b00 00000020 00000018 00000008 RWIX
ADCB_RESULT 00000b20 00000020 00000018 00000008 RWIX
ADCC_RESULT 00000b40 00000020 00000018 00000008 RWIX
ADCD_RESULT 00000b60 00000020 00000018 00000008 RWIX
CPU_TIMER0 00000c00 00000008 00000008 00000000 RWIX
CPU_TIMER1 00000c08 00000008 00000008 00000000 RWIX
CPU_TIMER2 00000c10 00000008 00000008 00000000 RWIX
PIE_CTRL 00000ce0 00000020 0000001a 00000006 RWIX
PIE_VECT 00000d00 00000200 000001c0 00000040 RWIX
DMA 00001000 00000200 000000e0 00000120 RWIX
CLA1 00001400 00000040 0000003e 00000002 RWIX
CLA1_MSGRAMLOW 00001480 00000080 00000036 0000004a RWIX
CLA1_MSGRAMHIGH 00001500 00000080 00000050 00000030 RWIX
EPWM1 00004000 00000100 00000100 00000000 RWIX
EPWM2 00004100 00000100 00000100 00000000 RWIX
EPWM3 00004200 00000100 00000100 00000000 RWIX
EPWM4 00004300 00000100 00000100 00000000 RWIX
EPWM5 00004400 00000100 00000100 00000000 RWIX
EPWM6 00004500 00000100 00000100 00000000 RWIX
EPWM7 00004600 00000100 00000100 00000000 RWIX
EPWM8 00004700 00000100 00000100 00000000 RWIX
EPWM9 00004800 00000100 00000100 00000000 RWIX
EPWM10 00004900 00000100 00000100 00000000 RWIX
EPWM11 00004a00 00000100 00000100 00000000 RWIX
EPWM12 00004b00 00000100 00000100 00000000 RWIX
ECAP1 00005000 00000020 00000020 00000000 RWIX
ECAP2 00005020 00000020 00000020 00000000 RWIX
ECAP3 00005040 00000020 00000020 00000000 RWIX
ECAP4 00005060 00000020 00000020 00000000 RWIX
ECAP5 00005080 00000020 00000020 00000000 RWIX
ECAP6 000050a0 00000020 00000020 00000000 RWIX
EQEP1 00005100 00000040 00000022 0000001e RWIX
EQEP2 00005140 00000040 00000022 0000001e RWIX
EQEP3 00005180 00000040 00000022 0000001e RWIX
DACA 00005c00 00000010 00000008 00000008 RWIX
DACB 00005c10 00000010 00000008 00000008 RWIX
DACC 00005c20 00000010 00000008 00000008 RWIX
CMPSS1 00005c80 00000020 00000020 00000000 RWIX
CMPSS2 00005ca0 00000020 00000020 00000000 RWIX
CMPSS3 00005cc0 00000020 00000020 00000000 RWIX
CMPSS4 00005ce0 00000020 00000020 00000000 RWIX
CMPSS5 00005d00 00000020 00000020 00000000 RWIX
CMPSS6 00005d20 00000020 00000020 00000000 RWIX
CMPSS7 00005d40 00000020 00000020 00000000 RWIX
CMPSS8 00005d60 00000020 00000020 00000000 RWIX
SDFM1 00005e00 00000080 00000080 00000000 RWIX
SDFM2 00005e80 00000080 00000080 00000000 RWIX
MCBSPA 00006000 00000040 00000024 0000001c RWIX
MCBSPB 00006040 00000040 00000024 0000001c RWIX
SPIA 00006100 00000010 00000010 00000000 RWIX
SPIB 00006110 00000010 00000010 00000000 RWIX
*** 00006120 00000010 00000010 00000000 RWIX
SPID 00006130 00000010 00000000 00000010 RWIX
UPP 00006200 00000100 00000000 00000100 RWIX
WD 00007000 00000040 0000002b 00000015 RWIX
NMIINTRUPT 00007060 00000010 00000007 00000009 RWIX
XINT 00007070 00000010 0000000b 00000005 RWIX
SCIA 00007200 00000010 00000010 00000000 RWIX
SCIB 00007210 00000010 00000010 00000000 RWIX
SCIC 00007220 00000010 00000010 00000000 RWIX
SCID 00007230 00000010 00000010 00000000 RWIX
I2CA 00007300 00000040 00000022 0000001e RWIX
I2CB 00007340 00000040 00000022 0000001e RWIX
ADCA 00007400 00000080 00000080 00000000 RWIX
ADCB 00007480 00000080 00000080 00000000 RWIX
ADCC 00007500 00000080 00000080 00000000 RWIX
ADCD 00007580 00000080 00000080 00000000 RWIX
INPUT_XBAR 00007900 00000020 00000000 00000020 RWIX
XBAR 00007920 00000020 00000000 00000020 RWIX
SYNC_SOC 00007940 00000010 00000000 00000010 RWIX
DMACLASRCSEL 00007980 00000040 0000001a 00000026 RWIX
EPWM_XBAR 00007a00 00000040 00000000 00000040 RWIX
CLB_XBAR 00007a40 00000040 00000000 00000040 RWIX
OUTPUT_XBAR 00007a80 00000040 00000000 00000040 RWIX
GPIOCTRL 00007c00 00000180 00000000 00000180 RWIX
GPIODAT 00007f00 00000030 00000030 00000000 RWIX
RAMLS4 0000a000 00000800 000004b4 0000034c RWIX
RAMLS5 0000a800 00000800 00000467 00000399 RWIX
RAMD1 0000b800 00000800 00000000 00000800 RWIX
RAMGS6_TO_11 00012000 00006000 00000000 00006000 RWIX
RAMGS12 00018000 00001000 00000000 00001000 RWIX
RAMGS13 00019000 00001000 00000000 00001000 RWIX
EMIF1 00047000 00000800 00000070 00000790 RWIX
EMIF2 00047800 00000800 00000070 00000790 RWIX
CANA 00048000 00000800 00000000 00000800 RWIX
CANA_MSG_RAM 00049000 00000800 00000000 00000800 RWIX
CANB 0004a000 00000800 00000000 00000800 RWIX
CANB_MSG_RAM 0004b000 00000800 00000000 00000800 RWIX
IPC 00050000 00000024 00000024 00000000 RWIX
FLASHPUMPSEMAPHORE 00050024 00000002 00000002 00000000 RWIX
DEV_CFG 0005d000 00000180 00000000 00000180 RWIX
ANALOG_SUBSYS 0005d180 00000080 00000000 00000080 RWIX
CLK_CFG 0005d200 00000100 00000032 000000ce RWIX
CPU_SYS 0005d300 00000100 00000082 0000007e RWIX
ROMPREFETCH 0005e608 00000002 00000000 00000002 RWIX
DCSM_Z1 0005f000 00000030 00000024 0000000c RWIX
DCSM_Z2 0005f040 00000030 00000024 0000000c RWIX
DCSM_COMMON 0005f070 00000010 00000008 00000008 RWIX
MEMCFG 0005f400 00000080 00000080 00000000 RWIX
EMIF1CONFIG 0005f480 00000020 00000020 00000000 RWIX
EMIF2CONFIG 0005f4a0 00000020 00000000 00000020 RWIX
ACCESSPROTECTION 0005f4c0 00000040 00000040 00000000 RWIX
MEMORYERROR 0005f500 00000040 00000040 00000000 RWIX
ROMWAITSTATE 0005f540 00000002 00000000 00000002 RWIX
FLASH0_CTRL 0005f800 00000300 00000182 0000017e RWIX
FLASH0_ECC 0005fb00 00000040 00000028 00000018 RWIX
DCSM_Z1_OTP 00078000 00000020 00000020 00000000 RWIX
DCSM_Z2_OTP 00078200 00000020 00000020 00000000 RWIX
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.TI.ramfunc
* 0 000002c0 00000004
000002c0 00000004 F2837xD_usDelay_CPU2.obj (.TI.ramfunc)
SHARERAMGS14_STR
* 0 0001a000 00000022 UNINITIALIZED
0001a000 00000022 Main_CPU2.obj (SHARERAMGS14_STR)
SHARERAMGS14_ADC
* 0 0001a800 00000020 UNINITIALIZED
0001a800 00000020 Main_CPU2.obj (SHARERAMGS14_ADC)
SHARERAMGS15_STR
* 0 0001b000 0000002c UNINITIALIZED
0001b000 0000002c Main_CPU2.obj (SHARERAMGS15_STR)
AdcaResultFile
* 1 00000b00 00000018 UNINITIALIZED
00000b00 00000018 F2837xD_GlobalVariableDefs_CPU2.obj (AdcaResultFile)
AdcbResultFile
* 1 00000b20 00000018 UNINITIALIZED
00000b20 00000018 F2837xD_GlobalVariableDefs_CPU2.obj (AdcbResultFile)
AdccResultFile
* 1 00000b40 00000018 UNINITIALIZED
00000b40 00000018 F2837xD_GlobalVariableDefs_CPU2.obj (AdccResultFile)
AdcdResultFile
* 1 00000b60 00000018 UNINITIALIZED
00000b60 00000018 F2837xD_GlobalVariableDefs_CPU2.obj (AdcdResultFile)
CpuTimer0RegsFile
* 1 00000c00 00000008 UNINITIALIZED
00000c00 00000008 F2837xD_GlobalVariableDefs_CPU2.obj (CpuTimer0RegsFile)
CpuTimer1RegsFile
* 1 00000c08 00000008 UNINITIALIZED
00000c08 00000008 F2837xD_GlobalVariableDefs_CPU2.obj (CpuTimer1RegsFile)
CpuTimer2RegsFile
* 1 00000c10 00000008 UNINITIALIZED
00000c10 00000008 F2837xD_GlobalVariableDefs_CPU2.obj (CpuTimer2RegsFile)
PieCtrlRegsFile
* 1 00000ce0 0000001a UNINITIALIZED
00000ce0 0000001a F2837xD_GlobalVariableDefs_CPU2.obj (PieCtrlRegsFile)
PieVectTableFile
* 1 00000d00 000001c0 UNINITIALIZED
00000d00 000001c0 F2837xD_GlobalVariableDefs_CPU2.obj (PieVectTableFile)
EmuKeyVar
* 1 00000d00 00000001 UNINITIALIZED
00000d00 00000001 F2837xD_GlobalVariableDefs_CPU2.obj (EmuKeyVar)
EmuBModeVar
* 1 00000d01 00000001 UNINITIALIZED
00000d01 00000001 F2837xD_GlobalVariableDefs_CPU2.obj (EmuBModeVar)
FlashCallbackVar
* 1 00000d02 00000000 UNINITIALIZED
FlashScalingVar
* 1 00000d02 00000000 UNINITIALIZED
DmaRegsFile
* 1 00001000 000000e0 UNINITIALIZED
00001000 000000e0 F2837xD_GlobalVariableDefs_CPU2.obj (DmaRegsFile)
EPwm1RegsFile
* 1 00004000 00000100 UNINITIALIZED
00004000 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm1RegsFile)
EPwm2RegsFile
* 1 00004100 00000100 UNINITIALIZED
00004100 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm2RegsFile)
EPwm3RegsFile
* 1 00004200 00000100 UNINITIALIZED
00004200 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm3RegsFile)
EPwm4RegsFile
* 1 00004300 00000100 UNINITIALIZED
00004300 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm4RegsFile)
EPwm5RegsFile
* 1 00004400 00000100 UNINITIALIZED
00004400 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm5RegsFile)
EPwm6RegsFile
* 1 00004500 00000100 UNINITIALIZED
00004500 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm6RegsFile)
EPwm7RegsFile
* 1 00004600 00000100 UNINITIALIZED
00004600 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm7RegsFile)
EPwm8RegsFile
* 1 00004700 00000100 UNINITIALIZED
00004700 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm8RegsFile)
EPwm9RegsFile
* 1 00004800 00000100 UNINITIALIZED
00004800 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm9RegsFile)
EPwm10RegsFile
* 1 00004900 00000100 UNINITIALIZED
00004900 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm10RegsFile)
EPwm11RegsFile
* 1 00004a00 00000100 UNINITIALIZED
00004a00 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm11RegsFile)
EPwm12RegsFile
* 1 00004b00 00000100 UNINITIALIZED
00004b00 00000100 F2837xD_GlobalVariableDefs_CPU2.obj (EPwm12RegsFile)
ECap1RegsFile
* 1 00005000 00000020 UNINITIALIZED
00005000 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (ECap1RegsFile)
ECap2RegsFile
* 1 00005020 00000020 UNINITIALIZED
00005020 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (ECap2RegsFile)
ECap3RegsFile
* 1 00005040 00000020 UNINITIALIZED
00005040 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (ECap3RegsFile)
ECap4RegsFile
* 1 00005060 00000020 UNINITIALIZED
00005060 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (ECap4RegsFile)
ECap5RegsFile
* 1 00005080 00000020 UNINITIALIZED
00005080 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (ECap5RegsFile)
ECap6RegsFile
* 1 000050a0 00000020 UNINITIALIZED
000050a0 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (ECap6RegsFile)
DacaRegsFile
* 1 00005c00 00000008 UNINITIALIZED
00005c00 00000008 F2837xD_GlobalVariableDefs_CPU2.obj (DacaRegsFile)
DacbRegsFile
* 1 00005c10 00000008 UNINITIALIZED
00005c10 00000008 F2837xD_GlobalVariableDefs_CPU2.obj (DacbRegsFile)
DaccRegsFile
* 1 00005c20 00000008 UNINITIALIZED
00005c20 00000008 F2837xD_GlobalVariableDefs_CPU2.obj (DaccRegsFile)
Sdfm1RegsFile
* 1 00005e00 00000080 UNINITIALIZED
00005e00 00000080 F2837xD_GlobalVariableDefs_CPU2.obj (Sdfm1RegsFile)
Sdfm2RegsFile
* 1 00005e80 00000080 UNINITIALIZED
00005e80 00000080 F2837xD_GlobalVariableDefs_CPU2.obj (Sdfm2RegsFile)
SpiaRegsFile
* 1 00006100 00000010 UNINITIALIZED
00006100 00000010 F2837xD_GlobalVariableDefs_CPU2.obj (SpiaRegsFile)
SpibRegsFile
* 1 00006110 00000010 UNINITIALIZED
00006110 00000010 F2837xD_GlobalVariableDefs_CPU2.obj (SpibRegsFile)
SpicRegsFile
* 1 00006120 00000010 UNINITIALIZED
00006120 00000010 F2837xD_GlobalVariableDefs_CPU2.obj (SpicRegsFile)
AdcaRegsFile
* 1 00007400 00000080 UNINITIALIZED
00007400 00000080 F2837xD_GlobalVariableDefs_CPU2.obj (AdcaRegsFile)
AdcbRegsFile
* 1 00007480 00000080 UNINITIALIZED
00007480 00000080 F2837xD_GlobalVariableDefs_CPU2.obj (AdcbRegsFile)
AdccRegsFile
* 1 00007500 00000080 UNINITIALIZED
00007500 00000080 F2837xD_GlobalVariableDefs_CPU2.obj (AdccRegsFile)
AdcdRegsFile
* 1 00007580 00000080 UNINITIALIZED
00007580 00000080 F2837xD_GlobalVariableDefs_CPU2.obj (AdcdRegsFile)
Cla1RegsFile
* 1 00001400 0000003e UNINITIALIZED
00001400 0000003e F2837xD_GlobalVariableDefs_CPU2.obj (Cla1RegsFile)
Cla1SoftIntRegsFile
* 1 00000ce0 00000004 DSECT
00000ce0 00000004 F2837xD_GlobalVariableDefs_CPU2.obj (Cla1SoftIntRegsFile)
Cmpss1RegsFile
* 1 00005c80 00000020 UNINITIALIZED
00005c80 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Cmpss1RegsFile)
Cmpss2RegsFile
* 1 00005ca0 00000020 UNINITIALIZED
00005ca0 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Cmpss2RegsFile)
Cmpss3RegsFile
* 1 00005cc0 00000020 UNINITIALIZED
00005cc0 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Cmpss3RegsFile)
Cmpss4RegsFile
* 1 00005ce0 00000020 UNINITIALIZED
00005ce0 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Cmpss4RegsFile)
Cmpss5RegsFile
* 1 00005d00 00000020 UNINITIALIZED
00005d00 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Cmpss5RegsFile)
Cmpss6RegsFile
* 1 00005d20 00000020 UNINITIALIZED
00005d20 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Cmpss6RegsFile)
Cmpss7RegsFile
* 1 00005d40 00000020 UNINITIALIZED
00005d40 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Cmpss7RegsFile)
Cmpss8RegsFile
* 1 00005d60 00000020 UNINITIALIZED
00005d60 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Cmpss8RegsFile)
DmaClaSrcSelRegsFile
* 1 00007980 0000001a UNINITIALIZED
00007980 0000001a F2837xD_GlobalVariableDefs_CPU2.obj (DmaClaSrcSelRegsFile)
Emif1RegsFile
* 1 00047000 00000070 UNINITIALIZED
00047000 00000070 F2837xD_GlobalVariableDefs_CPU2.obj (Emif1RegsFile)
Emif2RegsFile
* 1 00047800 00000070 UNINITIALIZED
00047800 00000070 F2837xD_GlobalVariableDefs_CPU2.obj (Emif2RegsFile)
DcsmZ1RegsFile
* 1 0005f000 00000024 UNINITIALIZED
0005f000 00000024 F2837xD_GlobalVariableDefs_CPU2.obj (DcsmZ1RegsFile)
DcsmZ2RegsFile
* 1 0005f040 00000024 UNINITIALIZED
0005f040 00000024 F2837xD_GlobalVariableDefs_CPU2.obj (DcsmZ2RegsFile)
DcsmCommonRegsFile
* 1 0005f070 00000008 UNINITIALIZED
0005f070 00000008 F2837xD_GlobalVariableDefs_CPU2.obj (DcsmCommonRegsFile)
DcsmZ1OtpFile
* 1 00078000 00000020 NOLOAD SECTION
00078000 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (DcsmZ1OtpFile)
DcsmZ2OtpFile
* 1 00078200 00000020 NOLOAD SECTION
00078200 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (DcsmZ2OtpFile)
EQep1RegsFile
* 1 00005100 00000022 UNINITIALIZED
00005100 00000022 F2837xD_GlobalVariableDefs_CPU2.obj (EQep1RegsFile)
EQep2RegsFile
* 1 00005140 00000022 UNINITIALIZED
00005140 00000022 F2837xD_GlobalVariableDefs_CPU2.obj (EQep2RegsFile)
EQep3RegsFile
* 1 00005180 00000022 UNINITIALIZED
00005180 00000022 F2837xD_GlobalVariableDefs_CPU2.obj (EQep3RegsFile)
Flash0CtrlRegsFile
* 1 0005f800 00000182 UNINITIALIZED
0005f800 00000182 F2837xD_GlobalVariableDefs_CPU2.obj (Flash0CtrlRegsFile)
Flash0EccRegsFile
* 1 0005fb00 00000028 UNINITIALIZED
0005fb00 00000028 F2837xD_GlobalVariableDefs_CPU2.obj (Flash0EccRegsFile)
GpioDataRegsFile
* 1 00007f00 00000030 UNINITIALIZED
00007f00 00000030 F2837xD_GlobalVariableDefs_CPU2.obj (GpioDataRegsFile)
I2caRegsFile
* 1 00007300 00000022 UNINITIALIZED
00007300 00000022 F2837xD_GlobalVariableDefs_CPU2.obj (I2caRegsFile)
I2cbRegsFile
* 1 00007340 00000022 UNINITIALIZED
00007340 00000022 F2837xD_GlobalVariableDefs_CPU2.obj (I2cbRegsFile)
IpcRegsFile
* 1 00050000 00000024 UNINITIALIZED
00050000 00000024 F2837xD_GlobalVariableDefs_CPU2.obj (IpcRegsFile)
FlashPumpSemaphoreRegsFile
* 1 00050024 00000002 UNINITIALIZED
00050024 00000002 F2837xD_GlobalVariableDefs_CPU2.obj (FlashPumpSemaphoreRegsFile)
MemCfgRegsFile
* 1 0005f400 00000080 UNINITIALIZED
0005f400 00000080 F2837xD_GlobalVariableDefs_CPU2.obj (MemCfgRegsFile)
Emif1ConfigRegsFile
* 1 0005f480 00000020 UNINITIALIZED
0005f480 00000020 F2837xD_GlobalVariableDefs_CPU2.obj (Emif1ConfigRegsFile)
AccessProtectionRegsFile
* 1 0005f4c0 00000040 UNINITIALIZED
0005f4c0 00000040 F2837xD_GlobalVariableDefs_CPU2.obj (AccessProtectionRegsFile)
MemoryErrorRegsFile
* 1 0005f500 00000040 UNINITIALIZED
0005f500 00000040 F2837xD_GlobalVariableDefs_CPU2.obj (MemoryErrorRegsFile)
McbspaRegsFile
* 1 00006000 00000024 UNINITIALIZED
00006000 00000024 F2837xD_GlobalVariableDefs_CPU2.obj (McbspaRegsFile)
McbspbRegsFile
* 1 00006040 00000024 UNINITIALIZED
00006040 00000024 F2837xD_GlobalVariableDefs_CPU2.obj (McbspbRegsFile)
NmiIntruptRegsFile
* 1 00007060 00000007 UNINITIALIZED
00007060 00000007 F2837xD_GlobalVariableDefs_CPU2.obj (NmiIntruptRegsFile)
SciaRegsFile
* 1 00007200 00000010 UNINITIALIZED
00007200 00000010 F2837xD_GlobalVariableDefs_CPU2.obj (SciaRegsFile)
ScibRegsFile
* 1 00007210 00000010 UNINITIALIZED
00007210 00000010 F2837xD_GlobalVariableDefs_CPU2.obj (ScibRegsFile)
ScicRegsFile
* 1 00007220 00000010 UNINITIALIZED
00007220 00000010 F2837xD_GlobalVariableDefs_CPU2.obj (ScicRegsFile)
ScidRegsFile
* 1 00007230 00000010 UNINITIALIZED
00007230 00000010 F2837xD_GlobalVariableDefs_CPU2.obj (ScidRegsFile)
ClkCfgRegsFile
* 1 0005d200 00000032 UNINITIALIZED
0005d200 00000032 F2837xD_GlobalVariableDefs_CPU2.obj (ClkCfgRegsFile)
CpuSysRegsFile
* 1 0005d300 00000082 UNINITIALIZED
0005d300 00000082 F2837xD_GlobalVariableDefs_CPU2.obj (CpuSysRegsFile)
WdRegsFile
* 1 00007000 0000002b UNINITIALIZED
00007000 0000002b F2837xD_GlobalVariableDefs_CPU2.obj (WdRegsFile)
XintRegsFile
* 1 00007070 0000000b UNINITIALIZED
00007070 0000000b F2837xD_GlobalVariableDefs_CPU2.obj (XintRegsFile)
codestart
* 0 00000000 00000002
00000000 00000002 F2837xD_CodeStartBranch_CPU2.obj (codestart)
.cinit 0 00000080 00000227
00000080 0000020d Main_CPU2.obj (.cinit)
0000028d 0000000e rts2800_fpu32.lib : exit.c.obj (.cinit)
0000029b 00000005 : _lock.c.obj (.cinit:__lock)
000002a0 00000005 : _lock.c.obj (.cinit:__unlock)
000002a5 00000002 --HOLE-- [fill = 0]
.pinit 0 00000080 00000000 UNINITIALIZED
.switch 0 000002a8 00000018
000002a8 00000018 SM_DCDC_CPU2.obj (.switch:_SM_DCDC)
.reset 0 003fffc0 00000002 DSECT
003fffc0 00000002 rts2800_fpu32.lib : boot28.asm.obj (.reset)
.stack 1 00000400 00000100 UNINITIALIZED
00000400 00000100 --HOLE--
.ebss 1 0000a800 00000363 UNINITIALIZED
0000a800 00000340 Main_CPU2.obj (.ebss)
0000ab40 00000018 F2837xD_CpuTimers_CPU2.obj (.ebss)
0000ab58 00000006 rts2800_fpu32.lib : exit.c.obj (.ebss)
0000ab5e 00000002 : _lock.c.obj (.ebss:__lock)
0000ab60 00000002 : _lock.c.obj (.ebss:__unlock)
0000ab62 00000001 SM_INV_CPU2.obj (.ebss)
Cla1Prog 1 0000a000 000004b4
0000a000 0000037a CLA_code_CPU2.obj (Cla1Prog:_Cla2Task1)
0000a37a 000000d0 CLA_code_CPU2.obj (Cla1Prog:_Cla2Task2)
0000a44a 00000020 cla1_math_library_fpu32.lib : CLAsqrt.obj (Cla1Prog:_CLAsqrt)
0000a46a 0000001a : CLAdiv.obj (Cla1Prog:_CLAdiv)
0000a484 00000008 CLA_code_CPU2.obj (Cla1Prog:_Cla2Task3)
0000a48c 00000008 CLA_code_CPU2.obj (Cla1Prog:_Cla2Task4)
0000a494 00000008 CLA_code_CPU2.obj (Cla1Prog:_Cla2Task5)
0000a49c 00000008 CLA_code_CPU2.obj (Cla1Prog:_Cla2Task6)
0000a4a4 00000008 CLA_code_CPU2.obj (Cla1Prog:_Cla2Task7)
0000a4ac 00000008 CLA_code_CPU2.obj (Cla1Prog:_Cla2Task8)
Cla1ToCpuMsgRAM
* 1 00001480 00000036 UNINITIALIZED
00001480 00000036 Main_CPU2.obj (Cla1ToCpuMsgRAM)
CpuToCla1MsgRAM
* 1 00001500 00000050 UNINITIALIZED
00001500 00000050 Main_CPU2.obj (CpuToCla1MsgRAM)
CLAscratch
* 1 0000ab63 00000100 UNINITIALIZED
0000ab63 00000100 --HOLE--
.scratchpad
* 1 0000ac64 00000004 UNINITIALIZED
0000ac64 00000004 cla1_math_library_fpu32.lib : CLAdiv.obj (.scratchpad:Cla1Prog:_CLAdiv)
0000ac64 00000004 : CLAsqrt.obj (.scratchpad:Cla1Prog:_CLAsqrt)
.text.1 0 00008000 00000800
00008000 00000506 SM_DCDC_CPU2.obj (.text)
00008506 000002a6 ADC_CPU2.obj (.text)
000087ac 00000053 SM_IR_INV_CPU2.obj (.text)
000087ff 00000001 rts2800_fpu32.lib : startup.c.obj (.text)
.text.2 0 00008800 00000800
00008800 000004bf Loop_CPU2.obj (.text)
00008cbf 00000213 F2837xD_SysCtrl_CPU2.obj (.text)
00008ed2 000000dd F2837xD_Adc_CPU2.obj (.text)
00008faf 00000051 SharedRAM_CPU2.obj (.text)
.text.3 0 00009000 00000800
00009000 0000047e SM_INV_CPU2.obj (.text)
0000947e 000001e7 System_Config_CPU2.obj (.text)
00009665 00000182 Loop_CPU2.obj (.text:retain)
000097e7 00000019 rts2800_fpu32.lib : args_main.c.obj (.text)
.text.4 0 00009800 000007fd
00009800 00000435 Main_CPU2.obj (.text)
00009c35 0000007c F2837xD_CpuTimers_CPU2.obj (.text)
00009cb1 0000007c CLA_Settings_CPU2.obj (.text:retain)
00009d2d 00000072 SM_IR_DCDC_CPU2.obj (.text)
00009d9f 0000006d ADC_CPU2.obj (.text:retain)
00009e0c 00000066 CLA_Settings_CPU2.obj (.text)
00009e72 00000056 rts2800_fpu32.lib : boot28.asm.obj (.text)
00009ec8 0000003a F2837xD_Ipc_Driver_Util_CPU2.obj (.text)
00009f02 00000035 F2837xD_Gpio_CPU2.obj (.text)
00009f37 00000031 DAC_CPU2.obj (.text)
00009f68 00000029 rts2800_fpu32.lib : exit.c.obj (.text)
00009f91 00000028 F2837xD_PieCtrl_CPU2.obj (.text)
00009fb9 00000024 rts2800_fpu32.lib : cpy_tbl.c.obj (.text)
00009fdd 0000001e : memcpy.c.obj (.text)
00009ffb 00000002 : pre_init.c.obj (.text)
.text.5 0 0000b000 00000800
0000b000 00000585 F2837xD_DefaultISR_CPU2.obj (.text:retain)
0000b585 0000022b PWM_CPU2.obj (.text)
0000b7b0 00000041 SharedRAM_CPU2.obj (.text:retain)
0000b7f1 0000000f Interrupt_CPU2.obj (.text:retain)
.text.6 0 0000c000 00000029
0000c000 00000018 rts2800_fpu32.lib : ll_aox28.asm.obj (.text)
0000c018 00000009 : _lock.c.obj (.text)
0000c021 00000008 F2837xD_CodeStartBranch_CPU2.obj (.text)
MODULE SUMMARY
Module code initialized data uninitialized data
------ ---- ---------------- ------------------
.\
F2837xD_GlobalVariableDefs_CPU2.obj 0 0 6983
Main_CPU2.obj 1077 525 1076
Loop_CPU2.obj 1601 0 0
F2837xD_DefaultISR_CPU2.obj 1413 0 0
SM_DCDC_CPU2.obj 1286 24 0
SM_INV_CPU2.obj 1150 0 1
CLA_code_CPU2.obj 1146 0 0
ADC_CPU2.obj 787 0 0
PWM_CPU2.obj 555 0 0
F2837xD_SysCtrl_CPU2.obj 531 0 0
System_Config_CPU2.obj 487 0 0
CLA_Settings_CPU2.obj 226 0 0
F2837xD_Adc_CPU2.obj 221 0 0
F2837xD_CpuTimers_CPU2.obj 124 0 24
SharedRAM_CPU2.obj 146 0 0
SM_IR_DCDC_CPU2.obj 114 0 0
SM_IR_INV_CPU2.obj 83 0 0
F2837xD_Ipc_Driver_Util_CPU2.obj 58 0 0
F2837xD_Gpio_CPU2.obj 53 0 0
DAC_CPU2.obj 49 0 0
F2837xD_PieCtrl_CPU2.obj 40 0 0
Interrupt_CPU2.obj 15 0 0
F2837xD_CodeStartBranch_CPU2.obj 10 0 0
F2837xD_usDelay_CPU2.obj 4 0 0
+--+-------------------------------------+-------+------------------+--------------------+
Total: 11176 549 8084
C:/ti/ccsv8/tools/compiler/ti-cgt-c2000_18.1.1.LTS/lib/rts2800_fpu32.lib
boot28.asm.obj 86 0 0
exit.c.obj 41 14 6
cpy_tbl.c.obj 36 0 0
memcpy.c.obj 30 0 0
args_main.c.obj 25 0 0
ll_aox28.asm.obj 24 0 0
_lock.c.obj 9 10 4
pre_init.c.obj 2 0 0
startup.c.obj 1 0 0
+--+-------------------------------------+-------+------------------+--------------------+
Total: 254 24 10
D:/Sviluppo_FW/CCS8/PD1801FW002V01_CPU2-UPS_LC/cla1_math_library_fpu32.lib
CLAsqrt.obj 32 0 4
CLAdiv.obj 26 0 4
+--+-------------------------------------+-------+------------------+--------------------+
Total: 58 0 8
Stack: 0 0 256
+--+-------------------------------------+-------+------------------+--------------------+
Grand Total: 11488 573 8358
GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE
address data page name
-------- ---------------- ----
00000400 10 (00000400) __stack
00000b00 2c (00000b00) _AdcaResultRegs
00000b20 2c (00000b00) _AdcbResultRegs
00000b40 2d (00000b40) _AdccResultRegs
00000b60 2d (00000b40) _AdcdResultRegs
00000c00 30 (00000c00) _CpuTimer0Regs
00000c08 30 (00000c00) _CpuTimer1Regs
00000c10 30 (00000c00) _CpuTimer2Regs
00000ce0 33 (00000cc0) _Cla1SoftIntRegs
00000ce0 33 (00000cc0) _PieCtrlRegs
00000d00 34 (00000d00) _EmuKey
00000d00 34 (00000d00) _PieVectTable
00000d01 34 (00000d00) _EmuBMode
00001000 40 (00001000) _DmaRegs
00001400 50 (00001400) _Cla1Regs
00001480 52 (00001480) _cla2_output
00001482 52 (00001480) _voutY_pwr_ups
00001488 52 (00001480) _voutY_rms_inv
0000148e 52 (00001480) _voutY_pwr_em
00001494 52 (00001480) _voutY_rms_em
0000149a 52 (00001480) _voutY_rms_ups
000014a0 52 (00001480) _voutY_pwr_inv
000014a6 52 (00001480) _i_bridge_pwr_inv
000014ae 52 (00001480) _i_bridge_rms_inv
00001500 54 (00001500) _pll_ns_cla
00001502 54 (00001500) _cla2_input
00001504 54 (00001500) _cla2_breakpoint
00001506 54 (00001500) _voutY_calib_ups
0000150c 54 (00001500) _voutY_em
00001512 54 (00001500) _voutY_qs_ups
00001518 54 (00001500) _voutY_qs_inv
0000151e 54 (00001500) _voutY_calib_inv
00001524 54 (00001500) _voutY_calib_em
0000152a 54 (00001500) _voutY_ups
00001530 54 (00001500) _voutY_qs_em
00001536 54 (00001500) _voutY_inv
00001540 55 (00001540) _i_bridge_qs_inv
00001548 55 (00001540) _i_bridge_inv
00004000 100 (00004000) _EPwm1Regs
00004100 104 (00004100) _EPwm2Regs
00004200 108 (00004200) _EPwm3Regs
00004300 10c (00004300) _EPwm4Regs
00004400 110 (00004400) _EPwm5Regs
00004500 114 (00004500) _EPwm6Regs
00004600 118 (00004600) _EPwm7Regs
00004700 11c (00004700) _EPwm8Regs
00004800 120 (00004800) _EPwm9Regs
00004900 124 (00004900) _EPwm10Regs
00004a00 128 (00004a00) _EPwm11Regs
00004b00 12c (00004b00) _EPwm12Regs
00005000 140 (00005000) _ECap1Regs
00005020 140 (00005000) _ECap2Regs
00005040 141 (00005040) _ECap3Regs
00005060 141 (00005040) _ECap4Regs
00005080 142 (00005080) _ECap5Regs
000050a0 142 (00005080) _ECap6Regs
00005100 144 (00005100) _EQep1Regs
00005140 145 (00005140) _EQep2Regs
00005180 146 (00005180) _EQep3Regs
00005c00 170 (00005c00) _DacaRegs
00005c10 170 (00005c00) _DacbRegs
00005c20 170 (00005c00) _DaccRegs
00005c80 172 (00005c80) _Cmpss1Regs
00005ca0 172 (00005c80) _Cmpss2Regs
00005cc0 173 (00005cc0) _Cmpss3Regs
00005ce0 173 (00005cc0) _Cmpss4Regs
00005d00 174 (00005d00) _Cmpss5Regs
00005d20 174 (00005d00) _Cmpss6Regs
00005d40 175 (00005d40) _Cmpss7Regs
00005d60 175 (00005d40) _Cmpss8Regs
00005e00 178 (00005e00) _Sdfm1Regs
00005e80 17a (00005e80) _Sdfm2Regs
00006000 180 (00006000) _McbspaRegs
00006040 181 (00006040) _McbspbRegs
00006100 184 (00006100) _SpiaRegs
00006110 184 (00006100) _SpibRegs
00006120 184 (00006100) _SpicRegs
00007000 1c0 (00007000) _WdRegs
00007060 1c1 (00007040) _NmiIntruptRegs
00007070 1c1 (00007040) _XintRegs
00007200 1c8 (00007200) _SciaRegs
00007210 1c8 (00007200) _ScibRegs
00007220 1c8 (00007200) _ScicRegs
00007230 1c8 (00007200) _ScidRegs
00007300 1cc (00007300) _I2caRegs
00007340 1cd (00007340) _I2cbRegs
00007400 1d0 (00007400) _AdcaRegs
00007480 1d2 (00007480) _AdcbRegs
00007500 1d4 (00007500) _AdccRegs
00007580 1d6 (00007580) _AdcdRegs
00007980 1e6 (00007980) _DmaClaSrcSelRegs
00007f00 1fc (00007f00) _GpioDataRegs
0000a800 2a0 (0000a800) _sm_exit_soft_start_dcdc
0000a801 2a0 (0000a800) _sm_inrush_sw_timer
0000a802 2a0 (0000a800) _sm_inrush_batt_state
0000a803 2a0 (0000a800) _sm_exit_soft_start_inv
0000a804 2a0 (0000a800) _sm_num_changed_state
0000a805 2a0 (0000a800) _sm_idx_changed_state
0000a806 2a0 (0000a800) _sm_pwm_state_inv
0000a807 2a0 (0000a800) _sm_pwm_state_dcdc
0000a808 2a0 (0000a800) _sm_inrush_inv_state
0000a809 2a0 (0000a800) _sm_dcdc_cnt_block
0000a80a 2a0 (0000a800) _sm_dcdc_code_CPU2
0000a80b 2a0 (0000a800) _sm_dcdc_state_CPU2
0000a80c 2a0 (0000a800) _sm_dcdc_oldstate_CPU2
0000a80d 2a0 (0000a800) _sm_inv_xcode_CPU2
0000a80e 2a0 (0000a800) _sm_dcdc_xcode_CPU2
0000a80f 2a0 (0000a800) _sm_dcdc_pcode_CPU2
0000a810 2a0 (0000a800) _sm_dcdc_enable
0000a811 2a0 (0000a800) _sm_inv_enable
0000a812 2a0 (0000a800) _sm_memo_code
0000a813 2a0 (0000a800) _sm_bypass_var_0
0000a814 2a0 (0000a800) _sm_memo_old_state
0000a815 2a0 (0000a800) _sm_memo_new_state
0000a816 2a0 (0000a800) _sm_bt3_inv_start_prev
0000a817 2a0 (0000a800) _sm_bypass_var_1
0000a818 2a0 (0000a800) _sm_bt2_dcdc_start_prev
0000a819 2a0 (0000a800) _sm_memo_type
0000a81a 2a0 (0000a800) _log3_inv_flag
0000a81b 2a0 (0000a800) _log1_dcdc_flag
0000a81c 2a0 (0000a800) _log1_inv_flag
0000a81d 2a0 (0000a800) _log2_inv_flag
0000a81e 2a0 (0000a800) _sm_com_type
0000a81f 2a0 (0000a800) _sm_com_type_prev
0000a820 2a0 (0000a800) _log2_dcdc_flag
0000a821 2a0 (0000a800) _log3_dcdc_flag
0000a822 2a0 (0000a800) _sm_inv_state_CPU2
0000a823 2a0 (0000a800) _sm_inv_oldstate_CPU2
0000a824 2a0 (0000a800) _sm_inv_pcode_CPU2
0000a825 2a0 (0000a800) _sm_idx_snd_changed_state
0000a826 2a0 (0000a800) _sm_inv_cnt_block
0000a827 2a0 (0000a800) _sm_inv_code_CPU2
0000a828 2a0 (0000a800) _ss
0000a82a 2a0 (0000a800) _cc
0000a82c 2a0 (0000a800) _sinn
0000a82e 2a0 (0000a800) _cosn
0000a830 2a0 (0000a800) _kft
0000a832 2a0 (0000a800) _ptr_system_timers
0000a834 2a0 (0000a800) _sm_absolute_time
0000a836 2a0 (0000a800) _ptr_system_flags
0000a838 2a0 (0000a800) _system_flags
0000a83a 2a0 (0000a800) _duty_3lev_T_melt
0000a83c 2a0 (0000a800) _duty_3lev_S_melt
0000a83e 2a0 (0000a800) _ps_inv
0000a840 2a1 (0000a840) _pr_inv
0000a842 2a1 (0000a840) _pt_inv
0000a844 2a1 (0000a840) _kmod
0000a846 2a1 (0000a840) _aferr
0000a848 2a1 (0000a840) _ptr_pll_inv
0000a84a 2a1 (0000a840) _duty_3lev_R_melt
0000a84c 2a1 (0000a840) _sm_inrush_batt_timer
0000a84e 2a1 (0000a840) _ptr_cpu1_record
0000a850 2a1 (0000a840) _fw_version_CPU1
0000a852 2a1 (0000a840) _cpu1_set_flag_record
0000a854 2a1 (0000a840) _cpu2_get_flag_record
0000a856 2a1 (0000a840) _fw_version_CPU2
0000a858 2a1 (0000a840) _ptr_cpu2_record
0000a85a 2a1 (0000a840) _sm_inrush_inv_timer
0000a85c 2a1 (0000a840) _system_io_out
0000a85e 2a1 (0000a840) _sm_inv_timer
0000a860 2a1 (0000a840) _system_io_in
0000a862 2a1 (0000a840) _sm_dcdc_timer
0000a864 2a1 (0000a840) _park_params
0000a868 2a1 (0000a840) _duty_2lev
0000a86c 2a1 (0000a840) _clarke_params_2LEV
0000a872 2a1 (0000a840) _clarke_params_3LEV
0000a878 2a1 (0000a840) _voutY_clarke_inv
0000a880 2a2 (0000a880) _ADC_RESULT
0000a888 2a2 (0000a880) _ADC
0000a890 2a2 (0000a880) _DAC_PTR
0000a898 2a2 (0000a880) _duty_3lev
0000a8a4 2a2 (0000a880) _ePWM
0000a8c0 2a3 (0000a8c0) _cpu1_gsram_record
0000a900 2a4 (0000a900) _pll_inv
0000a940 2a5 (0000a940) _cpu2_gsram_record
0000a980 2a6 (0000a980) _system_timers
0000a9c0 2a7 (0000a9c0) _sm_changed_state
0000ab40 2ad (0000ab40) _CpuTimer1
0000ab48 2ad (0000ab40) _CpuTimer2
0000ab50 2ad (0000ab40) _CpuTimer0
0000ab58 2ad (0000ab40) ___TI_enable_exit_profile_output
0000ab5a 2ad (0000ab40) ___TI_cleanup_ptr
0000ab5c 2ad (0000ab40) ___TI_dtors_ptr
0000ab5e 2ad (0000ab40) __lock
0000ab60 2ad (0000ab40) __unlock
0000ab62 2ad (0000ab40) _i
0001a000 680 (0001a000) _cpu2_r_array
0001a800 6a0 (0001a800) _AD7490_params_buffer
0001b000 6c0 (0001b000) _cpu2_rw_array
00047000 11c0 (00047000) _Emif1Regs
00047800 11e0 (00047800) _Emif2Regs
00050000 1400 (00050000) _IpcRegs
00050024 1400 (00050000) _FlashPumpSemaphoreRegs
0005d200 1748 (0005d200) _ClkCfgRegs
0005d300 174c (0005d300) _CpuSysRegs
0005f000 17c0 (0005f000) _DcsmZ1Regs
0005f040 17c1 (0005f040) _DcsmZ2Regs
0005f070 17c1 (0005f040) _DcsmCommonRegs
0005f400 17d0 (0005f400) _MemCfgRegs
0005f480 17d2 (0005f480) _Emif1ConfigRegs
0005f4c0 17d3 (0005f4c0) _AccessProtectionRegs
0005f500 17d4 (0005f500) _MemoryErrorRegs
0005f800 17e0 (0005f800) _Flash0CtrlRegs
0005fb00 17ec (0005fb00) _Flash0EccRegs
00078000 1e00 (00078000) _DcsmZ1Otp
00078200 1e08 (00078200) _DcsmZ2Otp
GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
page address name
---- ------- ----
abs ffffffff .text
0 00009f68 C$$EXIT
abs 00000100 CLA_SCRATCHPAD_SIZE
0 0000c000 LL$$AND
0 0000c008 LL$$OR
0 0000c010 LL$$XOR
0 0001a800 _AD7490_params_buffer
1 0000a888 _ADC
0 0000b0be _ADCA1_ISR
0 0000b33e _ADCA2_ISR
0 0000b348 _ADCA3_ISR
0 0000b352 _ADCA4_ISR
0 0000b334 _ADCA_EVT_ISR
0 0000b0c8 _ADCB1_ISR
0 0000b366 _ADCB2_ISR
0 0000b370 _ADCB3_ISR
0 0000b37a _ADCB4_ISR
0 0000b35c _ADCB_EVT_ISR
0 0000b0d2 _ADCC1_ISR
0 0000b4ce _ADCC2_ISR
0 0000b4d8 _ADCC3_ISR
0 0000b4e2 _ADCC4_ISR
0 0000b4c4 _ADCC_EVT_ISR
0 00009d9f _ADCC_ISR_CPU2
0 0000b0f0 _ADCD1_ISR
0 0000b4f6 _ADCD2_ISR
0 0000b500 _ADCD3_ISR
0 0000b50a _ADCD4_ISR
0 0000b4ec _ADCD_EVT_ISR
1 0000a880 _ADC_RESULT
0 0000b546 _AUX_PLL_SLIP_ISR
1 0005f4c0 _AccessProtectionRegs
0 00008ed2 _AdcSetMode
1 00007400 _AdcaRegs
1 00000b00 _AdcaResultRegs
1 00007480 _AdcbRegs
1 00000b20 _AdcbResultRegs
1 00007500 _AdccRegs
1 00000b40 _AdccResultRegs
1 00007580 _AdcdRegs
1 00000b60 _AdcdResultRegs
0 00008eae _AuxAuxClkSel
0 00008e98 _AuxIntOsc2Sel
0 00008ea2 _AuxXtalOscSel
0 0000b30c _CANA0_ISR
0 0000b316 _CANA1_ISR
0 0000b320 _CANB0_ISR
0 0000b32a _CANB1_ISR
0 0000b384 _CLA1_1_ISR
0 0000b38e _CLA1_2_ISR
0 0000b398 _CLA1_3_ISR
0 0000b3a2 _CLA1_4_ISR
0 0000b3ac _CLA1_5_ISR
0 0000b3b6 _CLA1_6_ISR
0 0000b3c0 _CLA1_7_ISR
0 0000b3ca _CLA1_8_ISR
0 00009e0c _CLA2_ConfigMemory
0 00009e30 _CLA2_Init
0 0000b550 _CLA_OVERFLOW_ISR
0 0000b55a _CLA_UNDERFLOW_ISR
1 0000a46a _CLAdiv
1 0000a44a _CLAsqrt
0 00008f75 _CalAdcINL
1 00001400 _Cla1Regs
0 00000ce0 _Cla1SoftIntRegs
0 00009cb1 _Cla2Isr1
0 00009cc2 _Cla2Isr2
0 00009cd3 _Cla2Isr3
0 00009ce2 _Cla2Isr4
0 00009cf1 _Cla2Isr5
0 00009d00 _Cla2Isr6
0 00009d0f _Cla2Isr7
0 00009d1e _Cla2Isr8
1 0000a000 _Cla2Task1
1 0000a37a _Cla2Task2
1 0000a484 _Cla2Task3
1 0000a48c _Cla2Task4
1 0000a494 _Cla2Task5
1 0000a49c _Cla2Task6
1 0000a4a4 _Cla2Task7
1 0000a4ac _Cla2Task8
0 00008955 _Clarke_CPU2
0 00008986 _Clarke_Reverse_KSQRT6_CPU2
1 0005d200 _ClkCfgRegs
1 00005c80 _Cmpss1Regs
1 00005ca0 _Cmpss2Regs
1 00005cc0 _Cmpss3Regs
1 00005ce0 _Cmpss4Regs
1 00005d00 _Cmpss5Regs
1 00005d20 _Cmpss6Regs
1 00005d40 _Cmpss7Regs
1 00005d60 _Cmpss8Regs
0 00009c76 _ConfigCpuTimer
0 00008506 _ConfigureADC_CPU2
1 0005d300 _CpuSysRegs
1 0000ab50 _CpuTimer0
1 00000c00 _CpuTimer0Regs
1 0000ab40 _CpuTimer1
1 00000c08 _CpuTimer1Regs
1 0000ab48 _CpuTimer2
1 00000c10 _CpuTimer2Regs
0 00008e57 _CsmUnlock
0 00009f37 _DAC_Init
1 0000a890 _DAC_PTR
0 0000b014 _DATALOG_ISR
0 0000b258 _DMA_CH1_ISR
0 0000b262 _DMA_CH2_ISR
0 0000b26c _DMA_CH3_ISR
0 0000b276 _DMA_CH4_ISR
0 0000b280 _DMA_CH5_ISR
0 0000b28a _DMA_CH6_ISR
1 00005c00 _DacaRegs
1 00005c10 _DacbRegs
1 00005c20 _DaccRegs
1 0005f070 _DcsmCommonRegs
1 00078000 _DcsmZ1Otp
1 0005f000 _DcsmZ1Regs
1 00078200 _DcsmZ2Otp
1 0005f040 _DcsmZ2Regs
0 00008d81 _DisableDog
0 00008d42 _DisablePeripheralClocks
1 00007980 _DmaClaSrcSelRegs
1 00001000 _DmaRegs
0 0000b1ae _ECAP1_ISR
0 0000b1b8 _ECAP2_ISR
0 0000b1c2 _ECAP3_ISR
0 0000b1cc _ECAP4_ISR
0 0000b1d6 _ECAP5_ISR
0 0000b1e0 _ECAP6_ISR
1 00005000 _ECap1Regs
1 00005020 _ECap2Regs
1 00005040 _ECap3Regs
1 00005060 _ECap4Regs
1 00005080 _ECap5Regs
1 000050a0 _ECap6Regs
0 0000b514 _EMIF_ERROR_ISR
0 0000b56e _EMPTY_ISR
0 0000b028 _EMU_ISR
0 0000b46a _EPWM10_ISR
0 0000b442 _EPWM10_TZ_ISR
0 0000b474 _EPWM11_ISR
0 0000b44c _EPWM11_TZ_ISR
0 0000b47e _EPWM12_ISR
0 0000b456 _EPWM12_TZ_ISR
0 0000b15e _EPWM1_ISR
0 0000b10e _EPWM1_TZ_ISR
0 0000b168 _EPWM2_ISR
0 0000b118 _EPWM2_TZ_ISR
0 0000b172 _EPWM3_ISR
0 0000b122 _EPWM3_TZ_ISR
0 0000b17c _EPWM4_ISR
0 0000b12c _EPWM4_TZ_ISR
0 0000b186 _EPWM5_ISR
0 0000b136 _EPWM5_TZ_ISR
0 0000b190 _EPWM6_ISR
0 0000b140 _EPWM6_TZ_ISR
0 0000b19a _EPWM7_ISR
0 0000b14a _EPWM7_TZ_ISR
0 0000b1a4 _EPWM8_ISR
0 0000b154 _EPWM8_TZ_ISR
0 0000b460 _EPWM9_ISR
0 0000b438 _EPWM9_TZ_ISR
1 00004900 _EPwm10Regs
1 00004a00 _EPwm11Regs
1 00004b00 _EPwm12Regs
1 00004000 _EPwm1Regs
1 00004100 _EPwm2Regs
1 00004200 _EPwm3Regs
1 00004300 _EPwm4Regs
1 00004400 _EPwm5Regs
1 00004500 _EPwm6Regs
1 00004600 _EPwm7Regs
1 00004700 _EPwm8Regs
1 00004800 _EPwm9Regs
0 0000b1ea _EQEP1_ISR
0 0000b1f4 _EQEP2_ISR
0 0000b1fe _EQEP3_ISR
1 00005100 _EQep1Regs
1 00005140 _EQep2Regs
1 00005180 _EQep3Regs
1 0005f480 _Emif1ConfigRegs
1 00047000 _Emif1Regs
1 00047800 _Emif2Regs
1 00000d01 _EmuBMode
1 00000d00 _EmuKey
0 00009fb0 _EnableInterrupts
0 000002c0 _F28x_usDelay
0 0000b528 _FLASH_CORRECTABLE_ERROR_ISR
0 0000b3fc _FPU_OVERFLOW_ISR
0 0000b406 _FPU_UNDERFLOW_ISR
1 0005f800 _Flash0CtrlRegs
1 0005fb00 _Flash0EccRegs
1 00050024 _FlashPumpSemaphoreRegs
0 000089b5 _G1INVSQRT6_CPU2
0 00009f02 _GPIO_ReadPin
0 00009f19 _GPIO_WritePin
0 00009a09 _Get_DRV_FAN_FUSE_Signal
0 00009b1d _Get_Input_Signal
0 000099a8 _Get_RMS_Measure
1 00007f00 _GpioDataRegs
0 00008ecc _HALT
0 00008ecf _HIB
0 0000b29e _I2CA_FIFO_ISR
0 0000b294 _I2CA_ISR
0 0000b2b2 _I2CB_FIFO_ISR
0 0000b2a8 _I2CB_ISR
1 00007300 _I2caRegs
1 00007340 _I2cbRegs
0 00008eb8 _IDLE
0 0000b03c _ILLEGAL_ISR
0 0000b410 _IPC0_ISR
0 0000b41a _IPC1_ISR
0 0000b424 _IPC2_ISR
0 0000b42e _IPC3_ISR
0 00009efe _IPCGetBootStatus
0 00009edf _IPCLtoRFlagBusy
0 00009ef6 _IPCLtoRFlagClear
0 00009eee _IPCLtoRFlagSet
0 00009ec8 _IPCRtoLFlagAcknowledge
0 00009ed0 _IPCRtoLFlagBusy
0 0000b7b0 _IPC_GSRAM_isr
0 00008d8f _InitAuxPll
0 00009c35 _InitCpuTimers
0 0000b585 _InitEPwm_CPU2
0 00008cc4 _InitPeripheralClocks
0 00009f91 _InitPieCtrl
0 00008cbf _InitSysCtrl_CPU2
0 000094a0 _Init_GPIO_CPU2
0 0000987a _Init_Vars_CPU2
0 0000b7f1 _IntDefaultHandler
1 00050000 _IpcRegs
0 00009665 _Loop_Epwm7_ISR_CPU2
0 0000b230 _MCBSPA_RX_ISR
0 0000b23a _MCBSPA_TX_ISR
0 0000b244 _MCBSPB_RX_ISR
0 0000b24e _MCBSPB_TX_ISR
1 00006000 _McbspaRegs
1 00006040 _McbspbRegs
1 0005f400 _MemCfgRegs
1 0005f500 _MemoryErrorRegs
0 000089d7 _Mod2Lev_CPU2
0 00008ae9 _Mod3Lev_CPU2
0 0000b032 _NMI_ISR
0 0000b57b _NOTUSED_ISR
1 00007060 _NmiIntruptRegs
0 000088e4 _Osc_Test_CPU2
0 0000b564 _PIE_RESERVED_ISR
1 00000ce0 _PieCtrlRegs
1 00000d00 _PieVectTable
0 0000b532 _RAM_ACCESS_VIOLATION_ISR
0 0000b51e _RAM_CORRECTABLE_ERROR_ISR
0 0000b01e _RTOS_ISR
0 00008800 _Refresh_DAC_CPU2
0 00008d69 _ReleaseFlashPump
0 00008819 _Reset_OVC_EVT
0 0000b2e4 _SCIA_RX_ISR
0 0000b2ee _SCIA_TX_ISR
0 0000b2f8 _SCIB_RX_ISR
0 0000b302 _SCIB_TX_ISR
0 0000b2bc _SCIC_RX_ISR
0 0000b2c6 _SCIC_TX_ISR
0 0000b2d0 _SCID_RX_ISR
0 0000b2da _SCID_TX_ISR
0 0000b488 _SD1_ISR
0 0000b492 _SD2_ISR
0 00008000 _SM_DCDC
0 00009000 _SM_INV
0 000087ac _SM_IR_INV
0 00009d2d _SM_IR_dcdc
0 000098f6 _SM_Transition_To_CPU1
0 0000b208 _SPIA_RX_ISR
0 0000b212 _SPIA_TX_ISR
0 0000b21c _SPIB_RX_ISR
0 0000b226 _SPIB_TX_ISR
0 0000b49c _SPIC_RX_ISR
0 0000b4a6 _SPIC_TX_ISR
0 00008ec1 _STANDBY
0 0000b53c _SYS_PLL_SLIP_ISR
1 00007200 _SciaRegs
1 00007210 _ScibRegs
1 00007220 _ScicRegs
1 00007230 _ScidRegs
1 00005e00 _Sdfm1Regs
1 00005e80 _Sdfm2Regs
0 00008a43 _SectorSearch_AB_CPU2
0 00008a9a _SectorSearch_abc_CPU2
0 00008d5a _SeizeFlashPump
0 00008d73 _ServiceDog
0 00009971 _Set_Calib_Params
0 00009bad _Set_Output_Signal
0 0000852e _Setup_ADC_CPU2
0 000094f8 _Setup_PWM_CPU2
0 00009656 _Setup_Timer0_CPU2
0 00008fe6 _Shared_Ram_dataRead
0 00008faf _Shared_Ram_dataWrite
1 00006100 _SpiaRegs
1 00006110 _SpibRegs
1 00006120 _SpicRegs
0 00008e78 _SysIntOsc1Sel
0 00008e82 _SysIntOsc2Sel
0 00008e8c _SysXtalOscSel
0 0000947e _System_Config_CPU2
0 0000b0fa _TIMER0_ISR
0 0000b000 _TIMER1_ISR
0 0000b00a _TIMER2_ISR
0 0000b4b0 _UPPA_ISR
0 0000b4ba _USBA_ISR
0 0000b0a0 _USER10_ISR
0 0000b0aa _USER11_ISR
0 0000b0b4 _USER12_ISR
0 0000b046 _USER1_ISR
0 0000b050 _USER2_ISR
0 0000b05a _USER3_ISR
0 0000b064 _USER4_ISR
0 0000b06e _USER5_ISR
0 0000b078 _USER6_ISR
0 0000b082 _USER7_ISR
0 0000b08c _USER8_ISR
0 0000b096 _USER9_ISR
0 0000b3f2 _VCU_ISR
0 0000b104 _WAKE_ISR
1 00007000 _WdRegs
0 0000b0dc _XINT1_ISR
0 0000b0e6 _XINT2_ISR
0 0000b3d4 _XINT3_ISR
0 0000b3de _XINT4_ISR
0 0000b3e8 _XINT5_ISR
1 00007070 _XintRegs
1 00000500 __STACK_END
abs 00000100 __STACK_SIZE
1 0000ab5a ___TI_cleanup_ptr
1 0000ab5c ___TI_dtors_ptr
1 0000ab58 ___TI_enable_exit_profile_output
abs ffffffff ___TI_pprof_out_hndl
abs ffffffff ___TI_prof_data_size
abs ffffffff ___TI_prof_data_start
abs ffffffff ___binit__
abs ffffffff ___c_args__
0 00000080 ___cinit__
abs ffffffff ___etext__
abs ffffffff ___pinit__
abs ffffffff ___text__
0 000097e7 __args_main
1 0000ab5e __lock
0 0000c020 __nop
0 0000c01c __register_lock
0 0000c018 __register_unlock
1 00000400 __stack
0 000087ff __system_post_cinit
0 00009ffb __system_pre_init
1 0000ab60 __unlock
0 00009f68 _abort
1 0000a846 _aferr
0 00009e72 _c_int00
1 0000a82a _cc
1 00001504 _cla2_breakpoint
1 00001502 _cla2_input
1 00001480 _cla2_output
1 0000a86c _clarke_params_2LEV
1 0000a872 _clarke_params_3LEV
0 00009fb9 _copy_in
1 0000a82e _cosn
1 0000a8c0 _cpu1_gsram_record
1 0000a852 _cpu1_set_flag_record
1 0000a854 _cpu2_get_flag_record
1 0000a940 _cpu2_gsram_record
0 0001a000 _cpu2_r_array
0 0001b000 _cpu2_rw_array
1 0000a868 _duty_2lev
1 0000a898 _duty_3lev
1 0000a84a _duty_3lev_R_melt
1 0000a83c _duty_3lev_S_melt
1 0000a83a _duty_3lev_T_melt
1 0000a8a4 _ePWM
0 00008bcb _exec_pll_inv
0 00009f6a _exit
1 0000a850 _fw_version_CPU1
1 0000a856 _fw_version_CPU2
1 0000ab62 _i
1 00001548 _i_bridge_inv
1 000014a6 _i_bridge_pwr_inv
1 00001540 _i_bridge_qs_inv
1 000014ae _i_bridge_rms_inv
1 0000a830 _kft
1 0000a844 _kmod
1 0000a81b _log1_dcdc_flag
1 0000a81c _log1_inv_flag
1 0000a820 _log2_dcdc_flag
1 0000a81d _log2_inv_flag
1 0000a821 _log3_dcdc_flag
1 0000a81a _log3_inv_flag
0 00009800 _main
0 00009fdd _memcpy
1 0000a864 _park_params
0 00008c44 _pll_freq_inv
1 0000a900 _pll_inv
1 00001500 _pll_ns_cla
1 0000a840 _pr_inv
1 0000a83e _ps_inv
1 0000a842 _pt_inv
1 0000a84e _ptr_cpu1_record
1 0000a858 _ptr_cpu2_record
1 0000a848 _ptr_pll_inv
1 0000a836 _ptr_system_flags
1 0000a832 _ptr_system_timers
1 0000a82c _sinn
1 0000a834 _sm_absolute_time
1 0000a818 _sm_bt2_dcdc_start_prev
1 0000a816 _sm_bt3_inv_start_prev
1 0000a813 _sm_bypass_var_0
1 0000a817 _sm_bypass_var_1
1 0000a9c0 _sm_changed_state
1 0000a81e _sm_com_type
1 0000a81f _sm_com_type_prev
1 0000a809 _sm_dcdc_cnt_block
1 0000a80a _sm_dcdc_code_CPU2
1 0000a810 _sm_dcdc_enable
1 0000a80c _sm_dcdc_oldstate_CPU2
1 0000a80f _sm_dcdc_pcode_CPU2
1 0000a80b _sm_dcdc_state_CPU2
1 0000a862 _sm_dcdc_timer
1 0000a80e _sm_dcdc_xcode_CPU2
1 0000a800 _sm_exit_soft_start_dcdc
1 0000a803 _sm_exit_soft_start_inv
1 0000a805 _sm_idx_changed_state
1 0000a825 _sm_idx_snd_changed_state
1 0000a802 _sm_inrush_batt_state
1 0000a84c _sm_inrush_batt_timer
1 0000a808 _sm_inrush_inv_state
1 0000a85a _sm_inrush_inv_timer
1 0000a801 _sm_inrush_sw_timer
1 0000a826 _sm_inv_cnt_block
1 0000a827 _sm_inv_code_CPU2
1 0000a811 _sm_inv_enable
1 0000a823 _sm_inv_oldstate_CPU2
1 0000a824 _sm_inv_pcode_CPU2
1 0000a822 _sm_inv_state_CPU2
1 0000a85e _sm_inv_timer
1 0000a80d _sm_inv_xcode_CPU2
1 0000a812 _sm_memo_code
1 0000a815 _sm_memo_new_state
1 0000a814 _sm_memo_old_state
1 0000a819 _sm_memo_type
1 0000a804 _sm_num_changed_state
1 0000a807 _sm_pwm_state_dcdc
1 0000a806 _sm_pwm_state_inv
1 0000a828 _ss
1 0000a838 _system_flags
1 0000a860 _system_io_in
1 0000a85c _system_io_out
1 0000a980 _system_timers
1 00001524 _voutY_calib_em
1 0000151e _voutY_calib_inv
1 00001506 _voutY_calib_ups
1 0000a878 _voutY_clarke_inv
1 0000150c _voutY_em
1 00001536 _voutY_inv
1 0000148e _voutY_pwr_em
1 000014a0 _voutY_pwr_inv
1 00001482 _voutY_pwr_ups
1 00001530 _voutY_qs_em
1 00001518 _voutY_qs_inv
1 00001512 _voutY_qs_ups
1 00001494 _voutY_rms_em
1 00001488 _voutY_rms_inv
1 0000149a _voutY_rms_ups
1 0000152a _voutY_ups
abs ffffffff binit
0 00000080 cinit
0 00000000 code_start
abs ffffffff etext
abs ffffffff pinit
GLOBAL SYMBOLS: SORTED BY Symbol Address
page address name
---- ------- ----
0 00000000 code_start
0 00000080 ___cinit__
0 00000080 cinit
0 000002c0 _F28x_usDelay
0 00000ce0 _Cla1SoftIntRegs
0 00008000 _SM_DCDC
0 00008506 _ConfigureADC_CPU2
0 0000852e _Setup_ADC_CPU2
0 000087ac _SM_IR_INV
0 000087ff __system_post_cinit
0 00008800 _Refresh_DAC_CPU2
0 00008819 _Reset_OVC_EVT
0 000088e4 _Osc_Test_CPU2
0 00008955 _Clarke_CPU2
0 00008986 _Clarke_Reverse_KSQRT6_CPU2
0 000089b5 _G1INVSQRT6_CPU2
0 000089d7 _Mod2Lev_CPU2
0 00008a43 _SectorSearch_AB_CPU2
0 00008a9a _SectorSearch_abc_CPU2
0 00008ae9 _Mod3Lev_CPU2
0 00008bcb _exec_pll_inv
0 00008c44 _pll_freq_inv
0 00008cbf _InitSysCtrl_CPU2
0 00008cc4 _InitPeripheralClocks
0 00008d42 _DisablePeripheralClocks
0 00008d5a _SeizeFlashPump
0 00008d69 _ReleaseFlashPump
0 00008d73 _ServiceDog
0 00008d81 _DisableDog
0 00008d8f _InitAuxPll
0 00008e57 _CsmUnlock
0 00008e78 _SysIntOsc1Sel
0 00008e82 _SysIntOsc2Sel
0 00008e8c _SysXtalOscSel
0 00008e98 _AuxIntOsc2Sel
0 00008ea2 _AuxXtalOscSel
0 00008eae _AuxAuxClkSel
0 00008eb8 _IDLE
0 00008ec1 _STANDBY
0 00008ecc _HALT
0 00008ecf _HIB
0 00008ed2 _AdcSetMode
0 00008f75 _CalAdcINL
0 00008faf _Shared_Ram_dataWrite
0 00008fe6 _Shared_Ram_dataRead
0 00009000 _SM_INV
0 0000947e _System_Config_CPU2
0 000094a0 _Init_GPIO_CPU2
0 000094f8 _Setup_PWM_CPU2
0 00009656 _Setup_Timer0_CPU2
0 00009665 _Loop_Epwm7_ISR_CPU2
0 000097e7 __args_main
0 00009800 _main
0 0000987a _Init_Vars_CPU2
0 000098f6 _SM_Transition_To_CPU1
0 00009971 _Set_Calib_Params
0 000099a8 _Get_RMS_Measure
0 00009a09 _Get_DRV_FAN_FUSE_Signal
0 00009b1d _Get_Input_Signal
0 00009bad _Set_Output_Signal
0 00009c35 _InitCpuTimers
0 00009c76 _ConfigCpuTimer
0 00009cb1 _Cla2Isr1
0 00009cc2 _Cla2Isr2
0 00009cd3 _Cla2Isr3
0 00009ce2 _Cla2Isr4
0 00009cf1 _Cla2Isr5
0 00009d00 _Cla2Isr6
0 00009d0f _Cla2Isr7
0 00009d1e _Cla2Isr8
0 00009d2d _SM_IR_dcdc
0 00009d9f _ADCC_ISR_CPU2
0 00009e0c _CLA2_ConfigMemory
0 00009e30 _CLA2_Init
0 00009e72 _c_int00
0 00009ec8 _IPCRtoLFlagAcknowledge
0 00009ed0 _IPCRtoLFlagBusy
0 00009edf _IPCLtoRFlagBusy
0 00009eee _IPCLtoRFlagSet
0 00009ef6 _IPCLtoRFlagClear
0 00009efe _IPCGetBootStatus
0 00009f02 _GPIO_ReadPin
0 00009f19 _GPIO_WritePin
0 00009f37 _DAC_Init
0 00009f68 C$$EXIT
0 00009f68 _abort
0 00009f6a _exit
0 00009f91 _InitPieCtrl
0 00009fb0 _EnableInterrupts
0 00009fb9 _copy_in
0 00009fdd _memcpy
0 00009ffb __system_pre_init
0 0000b000 _TIMER1_ISR
0 0000b00a _TIMER2_ISR
0 0000b014 _DATALOG_ISR
0 0000b01e _RTOS_ISR
0 0000b028 _EMU_ISR
0 0000b032 _NMI_ISR
0 0000b03c _ILLEGAL_ISR
0 0000b046 _USER1_ISR
0 0000b050 _USER2_ISR
0 0000b05a _USER3_ISR
0 0000b064 _USER4_ISR
0 0000b06e _USER5_ISR
0 0000b078 _USER6_ISR
0 0000b082 _USER7_ISR
0 0000b08c _USER8_ISR
0 0000b096 _USER9_ISR
0 0000b0a0 _USER10_ISR
0 0000b0aa _USER11_ISR
0 0000b0b4 _USER12_ISR
0 0000b0be _ADCA1_ISR
0 0000b0c8 _ADCB1_ISR
0 0000b0d2 _ADCC1_ISR
0 0000b0dc _XINT1_ISR
0 0000b0e6 _XINT2_ISR
0 0000b0f0 _ADCD1_ISR
0 0000b0fa _TIMER0_ISR
0 0000b104 _WAKE_ISR
0 0000b10e _EPWM1_TZ_ISR
0 0000b118 _EPWM2_TZ_ISR
0 0000b122 _EPWM3_TZ_ISR
0 0000b12c _EPWM4_TZ_ISR
0 0000b136 _EPWM5_TZ_ISR
0 0000b140 _EPWM6_TZ_ISR
0 0000b14a _EPWM7_TZ_ISR
0 0000b154 _EPWM8_TZ_ISR
0 0000b15e _EPWM1_ISR
0 0000b168 _EPWM2_ISR
0 0000b172 _EPWM3_ISR
0 0000b17c _EPWM4_ISR
0 0000b186 _EPWM5_ISR
0 0000b190 _EPWM6_ISR
0 0000b19a _EPWM7_ISR
0 0000b1a4 _EPWM8_ISR
0 0000b1ae _ECAP1_ISR
0 0000b1b8 _ECAP2_ISR
0 0000b1c2 _ECAP3_ISR
0 0000b1cc _ECAP4_ISR
0 0000b1d6 _ECAP5_ISR
0 0000b1e0 _ECAP6_ISR
0 0000b1ea _EQEP1_ISR
0 0000b1f4 _EQEP2_ISR
0 0000b1fe _EQEP3_ISR
0 0000b208 _SPIA_RX_ISR
0 0000b212 _SPIA_TX_ISR
0 0000b21c _SPIB_RX_ISR
0 0000b226 _SPIB_TX_ISR
0 0000b230 _MCBSPA_RX_ISR
0 0000b23a _MCBSPA_TX_ISR
0 0000b244 _MCBSPB_RX_ISR
0 0000b24e _MCBSPB_TX_ISR
0 0000b258 _DMA_CH1_ISR
0 0000b262 _DMA_CH2_ISR
0 0000b26c _DMA_CH3_ISR
0 0000b276 _DMA_CH4_ISR
0 0000b280 _DMA_CH5_ISR
0 0000b28a _DMA_CH6_ISR
0 0000b294 _I2CA_ISR
0 0000b29e _I2CA_FIFO_ISR
0 0000b2a8 _I2CB_ISR
0 0000b2b2 _I2CB_FIFO_ISR
0 0000b2bc _SCIC_RX_ISR
0 0000b2c6 _SCIC_TX_ISR
0 0000b2d0 _SCID_RX_ISR
0 0000b2da _SCID_TX_ISR
0 0000b2e4 _SCIA_RX_ISR
0 0000b2ee _SCIA_TX_ISR
0 0000b2f8 _SCIB_RX_ISR
0 0000b302 _SCIB_TX_ISR
0 0000b30c _CANA0_ISR
0 0000b316 _CANA1_ISR
0 0000b320 _CANB0_ISR
0 0000b32a _CANB1_ISR
0 0000b334 _ADCA_EVT_ISR
0 0000b33e _ADCA2_ISR
0 0000b348 _ADCA3_ISR
0 0000b352 _ADCA4_ISR
0 0000b35c _ADCB_EVT_ISR
0 0000b366 _ADCB2_ISR
0 0000b370 _ADCB3_ISR
0 0000b37a _ADCB4_ISR
0 0000b384 _CLA1_1_ISR
0 0000b38e _CLA1_2_ISR
0 0000b398 _CLA1_3_ISR
0 0000b3a2 _CLA1_4_ISR
0 0000b3ac _CLA1_5_ISR
0 0000b3b6 _CLA1_6_ISR
0 0000b3c0 _CLA1_7_ISR
0 0000b3ca _CLA1_8_ISR
0 0000b3d4 _XINT3_ISR
0 0000b3de _XINT4_ISR
0 0000b3e8 _XINT5_ISR
0 0000b3f2 _VCU_ISR
0 0000b3fc _FPU_OVERFLOW_ISR
0 0000b406 _FPU_UNDERFLOW_ISR
0 0000b410 _IPC0_ISR
0 0000b41a _IPC1_ISR
0 0000b424 _IPC2_ISR
0 0000b42e _IPC3_ISR
0 0000b438 _EPWM9_TZ_ISR
0 0000b442 _EPWM10_TZ_ISR
0 0000b44c _EPWM11_TZ_ISR
0 0000b456 _EPWM12_TZ_ISR
0 0000b460 _EPWM9_ISR
0 0000b46a _EPWM10_ISR
0 0000b474 _EPWM11_ISR
0 0000b47e _EPWM12_ISR
0 0000b488 _SD1_ISR
0 0000b492 _SD2_ISR
0 0000b49c _SPIC_RX_ISR
0 0000b4a6 _SPIC_TX_ISR
0 0000b4b0 _UPPA_ISR
0 0000b4ba _USBA_ISR
0 0000b4c4 _ADCC_EVT_ISR
0 0000b4ce _ADCC2_ISR
0 0000b4d8 _ADCC3_ISR
0 0000b4e2 _ADCC4_ISR
0 0000b4ec _ADCD_EVT_ISR
0 0000b4f6 _ADCD2_ISR
0 0000b500 _ADCD3_ISR
0 0000b50a _ADCD4_ISR
0 0000b514 _EMIF_ERROR_ISR
0 0000b51e _RAM_CORRECTABLE_ERROR_ISR
0 0000b528 _FLASH_CORRECTABLE_ERROR_ISR
0 0000b532 _RAM_ACCESS_VIOLATION_ISR
0 0000b53c _SYS_PLL_SLIP_ISR
0 0000b546 _AUX_PLL_SLIP_ISR
0 0000b550 _CLA_OVERFLOW_ISR
0 0000b55a _CLA_UNDERFLOW_ISR
0 0000b564 _PIE_RESERVED_ISR
0 0000b56e _EMPTY_ISR
0 0000b57b _NOTUSED_ISR
0 0000b585 _InitEPwm_CPU2
0 0000b7b0 _IPC_GSRAM_isr
0 0000b7f1 _IntDefaultHandler
0 0000c000 LL$$AND
0 0000c008 LL$$OR
0 0000c010 LL$$XOR
0 0000c018 __register_unlock
0 0000c01c __register_lock
0 0000c020 __nop
0 0001a000 _cpu2_r_array
0 0001a800 _AD7490_params_buffer
0 0001b000 _cpu2_rw_array
1 00000400 __stack
1 00000500 __STACK_END
1 00000b00 _AdcaResultRegs
1 00000b20 _AdcbResultRegs
1 00000b40 _AdccResultRegs
1 00000b60 _AdcdResultRegs
1 00000c00 _CpuTimer0Regs
1 00000c08 _CpuTimer1Regs
1 00000c10 _CpuTimer2Regs
1 00000ce0 _PieCtrlRegs
1 00000d00 _EmuKey
1 00000d00 _PieVectTable
1 00000d01 _EmuBMode
1 00001000 _DmaRegs
1 00001400 _Cla1Regs
1 00001480 _cla2_output
1 00001482 _voutY_pwr_ups
1 00001488 _voutY_rms_inv
1 0000148e _voutY_pwr_em
1 00001494 _voutY_rms_em
1 0000149a _voutY_rms_ups
1 000014a0 _voutY_pwr_inv
1 000014a6 _i_bridge_pwr_inv
1 000014ae _i_bridge_rms_inv
1 00001500 _pll_ns_cla
1 00001502 _cla2_input
1 00001504 _cla2_breakpoint
1 00001506 _voutY_calib_ups
1 0000150c _voutY_em
1 00001512 _voutY_qs_ups
1 00001518 _voutY_qs_inv
1 0000151e _voutY_calib_inv
1 00001524 _voutY_calib_em
1 0000152a _voutY_ups
1 00001530 _voutY_qs_em
1 00001536 _voutY_inv
1 00001540 _i_bridge_qs_inv
1 00001548 _i_bridge_inv
1 00004000 _EPwm1Regs
1 00004100 _EPwm2Regs
1 00004200 _EPwm3Regs
1 00004300 _EPwm4Regs
1 00004400 _EPwm5Regs
1 00004500 _EPwm6Regs
1 00004600 _EPwm7Regs
1 00004700 _EPwm8Regs
1 00004800 _EPwm9Regs
1 00004900 _EPwm10Regs
1 00004a00 _EPwm11Regs
1 00004b00 _EPwm12Regs
1 00005000 _ECap1Regs
1 00005020 _ECap2Regs
1 00005040 _ECap3Regs
1 00005060 _ECap4Regs
1 00005080 _ECap5Regs
1 000050a0 _ECap6Regs
1 00005100 _EQep1Regs
1 00005140 _EQep2Regs
1 00005180 _EQep3Regs
1 00005c00 _DacaRegs
1 00005c10 _DacbRegs
1 00005c20 _DaccRegs
1 00005c80 _Cmpss1Regs
1 00005ca0 _Cmpss2Regs
1 00005cc0 _Cmpss3Regs
1 00005ce0 _Cmpss4Regs
1 00005d00 _Cmpss5Regs
1 00005d20 _Cmpss6Regs
1 00005d40 _Cmpss7Regs
1 00005d60 _Cmpss8Regs
1 00005e00 _Sdfm1Regs
1 00005e80 _Sdfm2Regs
1 00006000 _McbspaRegs
1 00006040 _McbspbRegs
1 00006100 _SpiaRegs
1 00006110 _SpibRegs
1 00006120 _SpicRegs
1 00007000 _WdRegs
1 00007060 _NmiIntruptRegs
1 00007070 _XintRegs
1 00007200 _SciaRegs
1 00007210 _ScibRegs
1 00007220 _ScicRegs
1 00007230 _ScidRegs
1 00007300 _I2caRegs
1 00007340 _I2cbRegs
1 00007400 _AdcaRegs
1 00007480 _AdcbRegs
1 00007500 _AdccRegs
1 00007580 _AdcdRegs
1 00007980 _DmaClaSrcSelRegs
1 00007f00 _GpioDataRegs
1 0000a000 _Cla2Task1
1 0000a37a _Cla2Task2
1 0000a44a _CLAsqrt
1 0000a46a _CLAdiv
1 0000a484 _Cla2Task3
1 0000a48c _Cla2Task4
1 0000a494 _Cla2Task5
1 0000a49c _Cla2Task6
1 0000a4a4 _Cla2Task7
1 0000a4ac _Cla2Task8
1 0000a800 _sm_exit_soft_start_dcdc
1 0000a801 _sm_inrush_sw_timer
1 0000a802 _sm_inrush_batt_state
1 0000a803 _sm_exit_soft_start_inv
1 0000a804 _sm_num_changed_state
1 0000a805 _sm_idx_changed_state
1 0000a806 _sm_pwm_state_inv
1 0000a807 _sm_pwm_state_dcdc
1 0000a808 _sm_inrush_inv_state
1 0000a809 _sm_dcdc_cnt_block
1 0000a80a _sm_dcdc_code_CPU2
1 0000a80b _sm_dcdc_state_CPU2
1 0000a80c _sm_dcdc_oldstate_CPU2
1 0000a80d _sm_inv_xcode_CPU2
1 0000a80e _sm_dcdc_xcode_CPU2
1 0000a80f _sm_dcdc_pcode_CPU2
1 0000a810 _sm_dcdc_enable
1 0000a811 _sm_inv_enable
1 0000a812 _sm_memo_code
1 0000a813 _sm_bypass_var_0
1 0000a814 _sm_memo_old_state
1 0000a815 _sm_memo_new_state
1 0000a816 _sm_bt3_inv_start_prev
1 0000a817 _sm_bypass_var_1
1 0000a818 _sm_bt2_dcdc_start_prev
1 0000a819 _sm_memo_type
1 0000a81a _log3_inv_flag
1 0000a81b _log1_dcdc_flag
1 0000a81c _log1_inv_flag
1 0000a81d _log2_inv_flag
1 0000a81e _sm_com_type
1 0000a81f _sm_com_type_prev
1 0000a820 _log2_dcdc_flag
1 0000a821 _log3_dcdc_flag
1 0000a822 _sm_inv_state_CPU2
1 0000a823 _sm_inv_oldstate_CPU2
1 0000a824 _sm_inv_pcode_CPU2
1 0000a825 _sm_idx_snd_changed_state
1 0000a826 _sm_inv_cnt_block
1 0000a827 _sm_inv_code_CPU2
1 0000a828 _ss
1 0000a82a _cc
1 0000a82c _sinn
1 0000a82e _cosn
1 0000a830 _kft
1 0000a832 _ptr_system_timers
1 0000a834 _sm_absolute_time
1 0000a836 _ptr_system_flags
1 0000a838 _system_flags
1 0000a83a _duty_3lev_T_melt
1 0000a83c _duty_3lev_S_melt
1 0000a83e _ps_inv
1 0000a840 _pr_inv
1 0000a842 _pt_inv
1 0000a844 _kmod
1 0000a846 _aferr
1 0000a848 _ptr_pll_inv
1 0000a84a _duty_3lev_R_melt
1 0000a84c _sm_inrush_batt_timer
1 0000a84e _ptr_cpu1_record
1 0000a850 _fw_version_CPU1
1 0000a852 _cpu1_set_flag_record
1 0000a854 _cpu2_get_flag_record
1 0000a856 _fw_version_CPU2
1 0000a858 _ptr_cpu2_record
1 0000a85a _sm_inrush_inv_timer
1 0000a85c _system_io_out
1 0000a85e _sm_inv_timer
1 0000a860 _system_io_in
1 0000a862 _sm_dcdc_timer
1 0000a864 _park_params
1 0000a868 _duty_2lev
1 0000a86c _clarke_params_2LEV
1 0000a872 _clarke_params_3LEV
1 0000a878 _voutY_clarke_inv
1 0000a880 _ADC_RESULT
1 0000a888 _ADC
1 0000a890 _DAC_PTR
1 0000a898 _duty_3lev
1 0000a8a4 _ePWM
1 0000a8c0 _cpu1_gsram_record
1 0000a900 _pll_inv
1 0000a940 _cpu2_gsram_record
1 0000a980 _system_timers
1 0000a9c0 _sm_changed_state
1 0000ab40 _CpuTimer1
1 0000ab48 _CpuTimer2
1 0000ab50 _CpuTimer0
1 0000ab58 ___TI_enable_exit_profile_output
1 0000ab5a ___TI_cleanup_ptr
1 0000ab5c ___TI_dtors_ptr
1 0000ab5e __lock
1 0000ab60 __unlock
1 0000ab62 _i
1 00047000 _Emif1Regs
1 00047800 _Emif2Regs
1 00050000 _IpcRegs
1 00050024 _FlashPumpSemaphoreRegs
1 0005d200 _ClkCfgRegs
1 0005d300 _CpuSysRegs
1 0005f000 _DcsmZ1Regs
1 0005f040 _DcsmZ2Regs
1 0005f070 _DcsmCommonRegs
1 0005f400 _MemCfgRegs
1 0005f480 _Emif1ConfigRegs
1 0005f4c0 _AccessProtectionRegs
1 0005f500 _MemoryErrorRegs
1 0005f800 _Flash0CtrlRegs
1 0005fb00 _Flash0EccRegs
1 00078000 _DcsmZ1Otp
1 00078200 _DcsmZ2Otp
abs 00000100 CLA_SCRATCHPAD_SIZE
abs 00000100 __STACK_SIZE
abs ffffffff .text
abs ffffffff ___TI_pprof_out_hndl
abs ffffffff ___TI_prof_data_size
abs ffffffff ___TI_prof_data_start
abs ffffffff ___binit__
abs ffffffff ___c_args__
abs ffffffff ___etext__
abs ffffffff ___pinit__
abs ffffffff ___text__
abs ffffffff binit
abs ffffffff etext
abs ffffffff pinit
[472 symbols]
