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[FAQ] What happens when I connect a logic device's output to a 50 ohm transmission line?

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Transmission lines cause a lot of confusion for engineers. I hope to clear up some of that here. I will break this up into a few sections, so if you already know something you can easily skip to the information you need to know.

** Just as a disclaimer, transmission lines are an extremely complex topic, and I could never cover everything related to them here. **

What is a transmission line?

For the purposes of this post, a transmission line is just a wire that has been designed to carry an electrical signal with minimal loss over relatively large distances. We typically see these in a few forms:

Stripline/microstrip: these are traces on a PCB. Any trace can become a transmission line if it gets long enough. These are the most common source of issues for system designers if transmission lines effects are not taken into account.

Coax cables: These are typically 50-Ω characteristic impedance cables designed specifically for matching RF signals to 50-Ω signal sources and 50-Ω loads. There are other impedances out there, however 50 Ω is the most common version. The transmission line consists of center conductor surrounded by an insulator, and then a tube of conductive material. The signal typically rides on the center conductor and the outer conductor is grounded.

Twisted Pair: These are exactly what they sound like - a pair of wires, usually with one signal and one ground, that are twisted together to form a double  helix. They are most commonly found in network cables like Cat5e. Network cables have a typical characteristic impedance of 100 Ω.

Parallel Line: These are any two wires in parallel, one with the signal and the other grounded (typically). The most common form of these is a ribbon cable, which just has a bunch of wires in parallel running from one location to another. They are not used as commonly today due to noise and interference concerns.

How long does a transmission line need to be before it starts acting like a transmission line?

Generally speaking for logic? 20 cm

This value is heavily related to the frequency content of a signal, so the faster your edges are, the smaller that number gets. Let's quickly cover what I mean by "frequency content."

Frequency content of a square wave

Any signal can be broken down into a series of sine waves, and square waves end up being an infinite series of sine waves summed together. There's a great explanation here if you're interested: https://en.wikipedia.org/wiki/Square_wave

So, in a real signal, the maximum edge rate is the primary control on the frequency content of the signal. Let's use a 1 MHz signal as an example.  Here's 3 square waves that are all 1 MHz signals:

Three 1 MHz signals, each with a different edge rate. Top to bottom: 100ns, 10ns, 1ns

I took the fourier transform of these, and found that the harmonics for the first signal already had already dropped below 0.5V after just 20 MHz, while the third signal still had a 0.518V component at 100 MHz.

The general rule of thumb for determining the bandwidth of a square wave is to use the transition time (t_t, 10% to 90%) of the signal in this equation:

BW = 0.35 / t_t

For the top waveform above, the bandwidth is expected to be 0.35 / 100ns = 3.5 MHz, while the last signal would be 0.35 / 1ns = 350 MHz.

This bandwidth frequency, and not the square wave frequency, is what we are referring to when we talk about the "frequency content" of a signal.

Typical logic signals have transition times between 1ns and 10ns, which puts the typical maximum bandwidth of a signal around 350 MHz.

The general rule of thumb for a transmission line to be considered 'long enough' to start acting like a transmission line is one quarter wavelength ( λ/4 ). To get wavelength we can use this equation for a quick approximation:

λ = c / BW = 300 Mm/s / 350 MHz = 0.857 m

λ/4 ~= 21.4 cm

In the world of under 350 MHz square-wave clock signals (which is where standard logic devices 'live'), a "long distance" is at least 21.4 cm. On many circuit boards and in many systems, 20 cm isn't that large of a distance, so you might start to see transmission line effects on your board.

What exactly does a 'characteristic impedance' mean?

The characteristic impedance of a transmission line is simply the ratio of voltage to current at any point in the transmission line. The proof of this is complex, so I won't explain here, however just know that when you see "50 Ω" on a transmission line, it DOES NOT mean that the line acts like a 50 Ω transistor. It means that the travelling waves on that line will have a ratio of voltage to current that is 50 Ω, after all, resistance as defined by Ohm's Law is just a ratio:

R = V / I

This has some very interesting implications, which will be covered in the next section.

What are these 'transmission line effects' that keep coming up?

When a signal travels over a transmission line, there is typically very little loss (which is why we use tranmsission lines), however there are some important effects to take note of.

First, signals can reflect on a transmission line if there is an impedance mismatch. From the previous section, we know that at -any point- on a transmission line, the voltage to current ratio will always be the same. What happens when you connect a resitor to the then of the transmission line, forcing it to have a different voltage to current ratio (say 50 Ω on the transmission line and a 100 Ω resistor at the load). When the ratio of voltage to current is different on the transmission line and at the load, this produces a reflected wave. If you are trying to deliver power to the load, like with a power line or a radio transmitter, this is a very bad thing --- however, in logic systems, typically it is not a major problem because we are trying to deliver information, not power.

Here's 3 more square waves, this time having different load terminations with the same input and characteristic impedances:

< this section in work  - please give me a couple hours to post the rest :) >


TMS320F28379D: Dual core control scheme with ADC and CLA and EPWM

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Part Number:TMS320F28379D

Hello everyone,

I want to use both cores to control different stages of a converter and I'm wondering a few things:

  • I remember reading something about ADC result registers having mirrors in both cores. Can someone confirm that both cores have independent access to the ADC Result Regs? Is there any risk of delay if both cores try to read them at the same time, like a round-robin scheme or such?
  • I found a few topics stating that CPU2 cannot be used to clock or configure the HRPWM modules. Is it possible nonetheless to configure EPWM + HRPWM on CPU1 and then have CPU2.CLA1 update CMPA/CMPAHR?

The initialization of the F28379D would go like so:

For the realtime control architecture I would like to achieve what is described in the following diagram. 

Is it possible and if not what is the recommended way to do something similar? I thought about only performing calculations in CPU2.CLA1 and passing back to CPU1 the values to write to the EPWM, but I'd rather avoid the overhead.

Cheers,

Pierre

TMS570LC4357: CPU interconnect and ECC error injection

TLC5955: How to use GSCLK input?

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Part Number:TLC5955

Hello, this is my first post!

I'm using 11 chained TLC5955 (to power my 176 RGB leds) controlled by a STM32F7, and I encounter difficulties to make the driver working.

For now I can only power 16 rgb leds with the first TLC5955, but as soon as I want to lit more leds, I have bad results (leds are clipping, wrong color, random led lit, ...)

This is the simple procedure of my driver on the STM32F7:

- I set the LATCH to LOW

- I disable the SPI and I force a clock and a SIN low level (bitbang) in order to update the register

- I enable the SPI and I send via SPI the 768 bits of my RGB values

... and I repeat this operation for my 10 TLC5955 left.

- When it's done, I set the LATCH to HIGH

Something I don't really understand from the datasheet is what is the GSCLK input for ?

It should send 65538 pulses from the beggining of this procedure, and end before the LATCH = HIGH ? 

DP83867IR: Trying to get DP83867 to auto negotiate.

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Part Number:DP83867IR

Phy is connected to a ZynqMP chip.  In uboot, mii dump produces:

ZynqMP> mii info c
PHY 0x0C: OUI = 0x80028, Model = 0x23, Rev = 0x01, 10baseT, HDX
ZynqMP> mii dump c 0
0. (1140) -- PHY control register --
(8000:0000) 0.15 = 0 reset
(4000:0000) 0.14 = 0 loopback
(2040:0040) 0. 6,13 = b10 speed selection = 1000 Mbps
(1000:1000) 0.12 = 1 A/N enable
(0800:0000) 0.11 = 0 power-down
(0400:0000) 0.10 = 0 isolate
(0200:0000) 0. 9 = 0 restart A/N
(0100:0100) 0. 8 = 1 duplex = full
(0080:0000) 0. 7 = 0 collision test enable
(003f:0000) 0. 5- 0 = 0 (reserved)


ZynqMP> mii dump c 1
1. (7949) -- PHY status register --
(8000:0000) 1.15 = 0 100BASE-T4 able
(4000:4000) 1.14 = 1 100BASE-X full duplex able
(2000:2000) 1.13 = 1 100BASE-X half duplex able
(1000:1000) 1.12 = 1 10 Mbps full duplex able
(0800:0800) 1.11 = 1 10 Mbps half duplex able
(0400:0000) 1.10 = 0 100BASE-T2 full duplex able
(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
(0100:0100) 1. 8 = 1 extended status
(0080:0000) 1. 7 = 0 (reserved)
(0040:0040) 1. 6 = 1 MF preamble suppression
(0020:0000) 1. 5 = 0 A/N complete
(0010:0000) 1. 4 = 0 remote fault
(0008:0008) 1. 3 = 1 A/N able
(0004:0000) 1. 2 = 0 link status
(0002:0000) 1. 1 = 0 jabber detect
(0001:0001) 1. 0 = 1 extended capabilities


ZynqMP> mii dump c 2
2. (2000) -- PHY ID 1 register --
(ffff:2000) 2.15- 0 = 8192 OUI portion


ZynqMP> mii dump c 3
3. (a231) -- PHY ID 2 register --
(fc00:a000) 3.15-10 = 40 OUI portion
(03f0:0230) 3. 9- 4 = 35 manufacturer part number
(000f:0001) 3. 3- 0 = 1 manufacturer rev. number


ZynqMP> mii dump c 4
4. (01e1) -- Autonegotiation advertisement register --
(8000:0000) 4.15 = 0 next page able
(4000:0000) 4.14 = 0 (reserved)
(2000:0000) 4.13 = 0 remote fault
(1000:0000) 4.12 = 0 (reserved)
(0800:0000) 4.11 = 0 asymmetric pause
(0400:0000) 4.10 = 0 pause enable
(0200:0000) 4. 9 = 0 100BASE-T4 able
(0100:0100) 4. 8 = 1 100BASE-TX full duplex able
(0080:0080) 4. 7 = 1 100BASE-TX able
(0040:0040) 4. 6 = 1 10BASE-T full duplex able
(0020:0020) 4. 5 = 1 10BASE-T able
(001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3


ZynqMP> mii dump c 5
5. (0000) -- Autonegotiation partner abilities register --
(8000:0000) 5.15 = 0 next page able
(4000:0000) 5.14 = 0 acknowledge
(2000:0000) 5.13 = 0 remote fault
(1000:0000) 5.12 = 0 (reserved)
(0800:0000) 5.11 = 0 asymmetric pause able
(0400:0000) 5.10 = 0 pause able
(0200:0000) 5. 9 = 0 100BASE-T4 able
(0100:0000) 5. 8 = 0 100BASE-X full duplex able
(0080:0000) 5. 7 = 0 100BASE-TX able
(0040:0000) 5. 6 = 0 10BASE-T full duplex able
(0020:0000) 5. 5 = 0 10BASE-T able
(001f:0000) 5. 4- 0 = 0 selector = ???

Cannot get the chip to auto negotiate at all.  Several cables, routers, and laptops tested.

Tried to force A/N with mii write  c 0 0x1340 with no luck.  

Is there something i can probe or check to debug this?

TMS570LC4357: PortA and PortB flash memory access

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Part Number:TMS570LC4357

Hello,

In Datasheet, it is mentionned there are two slave ports (Flash_PortA and Flash_PortB) to access to the flash memory.

To read in FPROM Bank0 and 1:

1- Which port is configured by default? Port A, PortB or  Both? if BOTH, how is it managed?

2- Is it necessary that Software configure the port Access? Which TMS registers must be used to configure it?

Best regards,

François

CCS/MSP432P401R: Sensor BoosterPack example "[bleThread] Warning! Unexpected Event 256" on S1 button click

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Part Number:MSP432P401R

Tool/software: Code Composer Studio

Hi

I am trying to run Sensor BoosterPack example on my MSP432P401R + CC2650 BoosterPack + Sensors BoosterPack stack. Whenever I press S1 button after launching Debug session - I get a message: "[bleThread] Warning! Unexpected Event 256".  As well in Terminal the stack can not get to idle state. Can You kindly help me please? Included the screenshot of my debug session and terminal.

Also I have followed all the instructions in this link: e2e.ti.com/.../680504

but my problem isn't solved yet, I am using:

1. simplelink_sdk_ble_plugin_1_40_00_42 

2. simplelink_msp432p4_sdk_2_10_00_14  , I had tried the latest version (simplelink_msp432p4_sdk_2_30_00_14) but it didn't work too.

3. I had the HEX image programmed onto the device prior to running the code example using the file in this path C:\ti\simplelink_sdk_ble_plugin_1_40_00_42\source\ti\snp\cc2650\simple_np_cc2650bp_uart_pm_sbl_2_02_01_18a_merge.hex  and following the instructions in this link "dev.ti.com/.../users_guide_simplelink_sdk_plugin.html"

What could be the problem ? Your help is appreciated.  

SN75DP130: Thermal issue

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Part Number:SN75DP130

Hello

              Customer test their own board then find out temperature of DP130 achieve 70~80 °C. Has any suggestion to solve higher temperature to DP130?  Has any higher temperature range solution to replace DP130? Thank you. 

BR

Patrick


TMS570LC4357: PBIST Selftest parameters in library V2.4.0

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Part Number:TMS570LC4357

Hello,

In documentation SafeTIDiagnosticLibrary-User'sGuide-v2.4.0.chm , we want to use library SL_Seltest_PBIST function.

It seems that PBIST_EXECUTE must be chosen  for memory type two-port and single-port, and PBIST_EXECUTE_OVERRIDE chosen for memory type ROM.

But when PBIST_EXECUTE_OVERRIDE is set, the parameter ramGroup is not used in the function, so we can’t select the RAM group we want to Test.

Can you explain the usage of the parameter testType and its possible values PBIST_EXECUTE and PBIST_EXECUTE_OVERRIDE?

Best regards,

François

Headphone amplifier

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Hello

                   Do we have any headphone amp solution to meet below specification? Thank you. 

                  

TXB0104: VIL sink current

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Part Number:TXB0104

Hello

             Do we have VIL sink current specification as below IOH/IOL? Thank you. 

  

BR

Patrick

CCS/CC1352R: EasyLink_getRssi() documentation

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Part Number:CC1352R

Tool/software: Code Composer Studio

Can anyone shed some light on the behavior of EasyLink_getRssi()?

I either get a good value or -128 (RF_GET_RSSI_ERROR_VAL). The documentation isn't entirely helpful as to why it does not work sometimes.

Side question: since EasyLink_getRssi() returns a EasyLink_Status, shouldn't that be something other than success when the rssi value it sets is clearly not valid?

What I am ultimately trying to do is assess the noisyness of the environment. Maybe there is a better way to go about this. I'd like to periodically sample the rssi without actually sending or receiving. I'm using EasyLink_transmitCcaAsync() and trying to assess the optimum EASYLINK_CS_RSSI_THRESHOLD_DBM

CCS/CC3220MOD: Boundary Scan and JTAG Interface CC3220MOD

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Part Number:CC3220MOD

Tool/software: Code Composer Studio

We have build three prototypes of our product which incorporates the CC3220MODA.
We have used a launchpad to program the code in to two of the three prototypes.  We put the target into SOP1 and applied power. We worred the U0 TX and TX from the launce pad to the target. We connected the JTAG interface from the Launchpad to the target.  We Power cycled the target and the launch pad and powerd on the target first.
We used UNIFLASH 4.40 to program the target in Development mode.

With the LAUNCHPAD as programer and debugger, we were able to read the MAC address on two of the three target hardware boards and program the CC3220MODA in Development mode.

We can not get the programmer to read the MAC address. It times out and reports an error:

I have verified proper 3.3Volts to the target. I have inspected the UAR and JTAG connections between the Launcpad and the target and found no errors.

I have no shorts on the JTAG interface.

I tried loading software in the blind (with out reading the MAC) in production mode but again the UNIFLASH times out.

Not sure what to try next.

Has anyone ever developed a boundary scan test for the JTAG interface and the UART0 interface necessary to program this part?  Anything to help us better localize the fault.

Compiler/TMS320C6713B: Compiler/TMS320C6713: Device not supported on Code Composer Studio v7.4 (CCSv7.4) TMS320C6713

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Part Number:TMS320C6713B

Tool/software: TI C/C++ Compiler

Hello,

            I have installed CCSv7.4_win32 on my PC. when i choose device TMS320C6713 in my new project, it says "The device is no longer supported by the compiler of version 8.0.0 or higher". Here, 7.4 compiler version option is not available in project settings. The snapshot of corresponding problem attached above. Anybody can resolve this problem.

    Thanking you,

TMS320F2811: TMS320F2811

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Part Number:TMS320F2811

good day I need an advice use the instrument for reading and writing over jtag.I anticipate for help in advance


CCS/UCD3138A64: Problem running the code for blinky in UCD3138A64.

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Part Number:UCD3138A64

Tool/software: Code Composer Studio

We are using code composer studio version 8. We loaded the training lab common source code for lab2 and made a few changes for it to run it as the blinky code. The code is being loaded as seen here but we are unable to click on the 'run' button. After loading the code they are asking us to set the preferences. Can you let us know why is this happening and on which memory location is the code actually being loaded.

RTOS/AWR1642BOOST: R165 Location

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Part Number:AWR1642BOOST

Tool/software: TI-RTOS

Before I solder on a 0 ohm resistor to enable the HW trigger on my AWR1642 ES1.0 device, I want to verify that this is the appropriate location for such a jumper. According to the schematic, R165 is here highlighted in blue:

On the device, that would correspond to this location (small green circle). From observation, it does not seem that there is a resistor present, so this would make sense. 

Could you please confirm this will work? Furthermore, will there be any issues capturing LVDS data from a connected DCA1000EVM if I solder a resistor in this place?

TMS320F280049C: Loading Program for Flash vs RAM

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Part Number:TMS320F280049C

Hi, I am generating a sine wave using DACA of a certain frequency. Sine table consists of 10 samples. I am a little bit confused that when I program the code in flash i get a different frequency at output and when I program the same code in RAM I should get the same frequency because the code is same, instead, I get a different frequency for the same code. Please guide me why is this happening.

Linux/L293D: Voltage Drop at Outputs

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Part Number:L293D

Tool/software: Linux

Hi,

I'm a French student working on an RC autonomous car project. The first part of the project consists in controlling two DC motors using Pulse With Modulation. I use the L293D with a Raspberry Pi 3B+.

I have a 7.2 V battery for the VCC2 and 5V from the RPi for the VCC1. I tried using PWM with the EN1 pin then with the IN1/2 pin (respectively EN2 and IN3/4 for the second engine). However, I still have the same problem.

When I run my code, a significant voltage drop occurs (between 3 and 4V). I can measure it at VCC1, VCC2 and at the outputs, even with a PWM at 100%. Therefore, my engines do not turn fast enough and I don't know how this voltage drop can be avoided.

Is it possible to avoid this voltage drop? Is the code the only problem, even though I tried two methods (sending PWM to the EN pin and using IN1/IN2 for the directions, or setting EN to High and using PWM on IN1 or IN2 depending on the direction)?

Thank you,

Piciu

CCS/TMDSDSK6713: Enabling SDRAM on DSP Kit DSK6713

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Part Number:TMDSDSK6713

Tool/software: Code Composer Studio

Hi. I am Ammar and working on a real time audio processing project on DSP Kit  DSK6713 . I need more memory for my Code and trying to use SDRAM but it gives an error because when I call malloc why does it return 0x000000 ? 

Gel file is attached. Kindly help if I need to make changes in the gel file. Kindly tell if any changes or any configuration is needed.

Regards

(Please visit the site to view this file)

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