Part Number:CC3120
Tool/software: Code Composer Studio
Traced the problem to the dependent project freertos_builds_MSP_EXP432P4111_release_ccsfile posix/pthread.c line 393:
status = xTaskCreate((TaskFunction_t)_pthread_runStub, NULL /* name */,
xTaskCreate calls prvInitialiseNewTask which has a configASSERT(pcName) where pcName is NULL
To get the demo running changed to:
status = xTaskCreate((TaskFunction_t)_pthread_runStub, "mainThread" /* name */,
What would be a 'proper' fix to this?
Part Number:TMDSSOLARUINVKIT
Tool/software: Code Composer Studio
All the time I want to test connection, I receive this message:
"One of the FTDI driver functions used during the connect
returned bad status or an error. The cause may be one or
more of: no XDS100 is plugged in, invalid XDS100 serial number,
blank XDS100 EEPROM, missing FTDI drivers, faulty USB cable.
Use the xds100serial command-line utility in the 'common/uscif'
folder to verify the XDS100 can be located.'
OK, I have installed FTDI; but nothing changed.
plz help me to solve this problem.
and when I change connection to "texas instrument xds100 v1 usb debug probe" I receive this one:
"
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 2, skipped: 0, failed: 1
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 2
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 3
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 4
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 5
Some of the values were corrupted - 83.3 percent.
The JTAG DR Integrity scan-test has failed.
[End: Texas Instruments XDS100v1 USB Debug Probe_0]"
Part Number:AM3352
Hi ,
I wonder if VDDSHV5 support 2.5V? I only saw 1.8V and 3.3V description on datasheet but i have a switch which's RGMII interface power by 2.5V.
Regards,
Part Number:ADS122U04
Hello I have a question on the schematic for the ADS122U04 EVM. For the setup for a 2-Wire RTD that is shown below there is a Resistor in the schematic R79 shown below as a 3.4K value resistor. The EVM User Manual indicates that this may need to be changed depending on the iDAC output current and R77 Value(4.7K on the EVM) that creates the VREF voltage. It is not clear how to determine an appropriate value for R79 based on changes that would be made to the IDAC output current and hence updated R77 value to create the desired VREF voltage?
Can someone please assist with the calculation to determine the correct value and also help with the understanding of the purpose of this resistor? The notes in Sect 5.1.1 of the EVM manual indicate R79 is to maintain proper common mode voltage when using the PGA gain but I am not really clear on my understanding of this. I understand what Common-Mode is and the PGA requirements for this.
My specifics are
Using the ADS1220
IDAC = 10 or 50uA depending on our specific NTC Thermistor
AVDD = 3.3V though may need to bump this up higher to accomodate IDAC compliance.
Any insight would be very helpful and welcomed...
Regards,
Frank
Part Number:LAUNCHXL-CC2640R2
Tool/software: Code Composer Studio
I contacted Ti with the following questions. They suggested posting on this forum.
I have a few questions about the LAUNCHXL-CC2640R2.
I’m looking at applications where I think the CC2640R2F would fit.
I’ve worked with other programming/microprocessors in the past (more Atmel based).
I downloaded Code Composer Studio (CCS), and was trying to “test-drive” it a little.
I think it could be inexperience on my part, but CCS didn’t seem to auto-complete well, or have good intellisense. When I type in a function, it seemed to recognize it was a function (would auto insert an open parenthesis), but did not offer help on what arguments should be passed to the function. I also does not seem to have intellisense.
I’m kind-of spoiled using visual studio (and similar IDEs), and was wondering if there is a better IDE. Perhaps I’m not experienced enough with CCS, or there is a better IDE I should try. I’ve used visual-studio based IDEs for other processors, and thought maybe TI had one.
I would like to avoid cloud-based IDEs (I’d like the IDE to run on my local CPU). This is due to the fact sometimes I need to work completely off the network. If needed, I could use a cloud-based IDE, but I think you see the challenges.
Thanks for any thoughts.
Part Number:CC2640R2F
Tool/software: Code Composer Studio
Hello,
I try to read the Characteristic Value from a Thermometer. I use the CC2640RF as a central, i make a BLE connection with the Thermometer and i wold like to read the "Temperature Measurement Characteristic".
How can I read the value?
// Temperature Measurement Characteristic defines
#define HT_TEMPERATURE_MEASUREMENT_ID 0
#define HT_TEMPERATURE_MEASUREMENT_UUID 0x2A1C
#define HT_TEMPERATURE_MEASUREMENT_LEN 20
#define HT_TEMPERATURE_MEASUREMENT_LEN_MIN
I use this code:
// Do a read
uint8_t status;
attReadReq_t req;
req.handle = (uint16)HT_TEMPERATURE_MEASUREMENT_UUID;
status = GATT_ReadCharValue(connHandle, &req, selfEntity);
if (status == SUCCESS)
{
Display_print0(dispHandle, 9, 0, "SUCCESS");
}
best reagrds,
Fares Rabuts
Part Number:TLV62150
Team,
I have a customer examining the TLV62150 for an upcoming design, and they want to know if it is ok to utilize any other type of capacitor apart from ceramic? From sections 9.2.2.2.2.1 and 2 of the datasheet, it looks like ceramic is chosen for the low ESR typically associated with these. If the customer takes ESR into account with their selection, is there any reason they could not use some other medium here?
Part Number:TMS320F28335
Tool/software: Code Composer Studio
Hi, I'm working on a project where I need to have the path to the hex binary file of the compiled project accessible from within the source code. We came up with a solution that works fine in Linux:
HEX_PATH=${PWD}/${BuildArtifactFileBaseName}.hex
This expands to /path/to/directory/blah.hex which appears to be a valid C macro.
In windows however, this expands to C:\path\to\directory/blah.hex and I get the following error during compilation:
Command-line error #1046: invalid macro definition: HEX_PATH=C:\path\to\directory/blah.hex
It appears this error is due to the C:\ portion of the definition. "path\to\directory/blah.hex" seems to be a valid definition.
I would like to avoid adding an additional configuration to the project just to handle this. We also don't need the path to be correct in windows, we just need it to compile.
One option I thought of was using a ternary operator but this syntax hasn't worked for me:
HEX_PATH= (${HostOsName}=="Linux" ? ${PWD}/${BuildArtifactFileBaseName}.hex : ${BuildArtifactFileBaseName}.hex)
Thoughts or suggestions on how to solve this would be appreciated.
Part Number:LAUNCHXL-F28069M
Tool/software: Code Composer Studio
Hello,
First time taking advantage of E2E...so bear with me if I forget to add something or leave out details.
I'm currently using a LAUNCHXL-f28069M with 2 BOOSTXL-DRV8301's in order to drive 2 3-phase brushless motors. The system setup is as follows:
Control Input: Joystick
Master Control: Arduino Teensy
Communication Protocol between Teensy & LAUNCHXL: Serial
Below is a snippet of the code added to the main() loop of proj_lab10d. There's an eStop added almost as an enable/disable. That appears to be 100% functional.
if(SCI_rxDataReady(halHandle->sciBHandle)== true)
{
sciInput = SCI_getDataBlocking(halHandle->sciBHandle);
eStopStatus = sciInput & 0x80;
motorSelected = sciInput & 0x40;
if(eStopStatus == 0)
{
//gSystemVars.Flag_enableSystem = false;
gMotorVars[HAL_MTR1].Flag_enableSys = false;
gMotorVars[HAL_MTR2].Flag_enableSys = false;
gMotorVars[HAL_MTR1].Flag_Run_Identify = false;
gMotorVars[HAL_MTR2].Flag_Run_Identify = false;
}
else
{
gMotorVars[HAL_MTR1].Flag_enableSys = true;
gMotorVars[HAL_MTR2].Flag_enableSys = true;
gMotorVars[HAL_MTR1].Flag_Run_Identify = true;
gMotorVars[HAL_MTR2].Flag_Run_Identify = true;
}
if(motorSelected == motorLeft)
{
leftMotorSpeed = sciInput & 0x3F; //bitmask the last 6 bits
if(leftMotorSpeed == 0b1)
{
gMotorVars[HAL_MTR1].SpeedRef_krpm = speedP1;
}
else if (leftMotorSpeed == 0b10)
{
gMotorVars[HAL_MTR1].SpeedRef_krpm = speedP2;
}
else if (leftMotorSpeed == 0b11)
{
gMotorVars[HAL_MTR1].SpeedRef_krpm = speedP3;
}
else if (leftMotorSpeed == 0b101)
{
gMotorVars[HAL_MTR1].SpeedRef_krpm = speedN1;
}
else if (leftMotorSpeed == 0b110)
{
gMotorVars[HAL_MTR1].SpeedRef_krpm = speedN2;
}
else if (leftMotorSpeed == 0b111)
{
gMotorVars[HAL_MTR1].SpeedRef_krpm = speedN3;
}
When the motor starts turning initially after getting info from the Teensy (Happens roughly every 30ms), the motor almost has a "tug of war", where it constantly jitters back and forth, until it eventually levels out.
When the input speed for the motors should be 0, they take ~7sec to decelerate and the jitter happens again close to 0 rpm. The tuning is done using the sensorless tuning provided by InstaSPIN. The motor controller receives 2 separate packets from the teensy, first is data for the left motor, then data for the right motor is sent. Above only shows the left motor just to save from code-dumping.
Would incorporating the hall effect sensors of the motor resolve this issue? And if I use them, should I disable the sensorless tuning? Also, what might the jitter be coming from? it seems to happen in a small interval right in the beginning of the ramp up and the end of the deceleration.
Let me know if there might be any other helpful information!
Part Number:TMS320F28035
Tool/software: Code Composer Studio
Dear,
I would like to run the SFRA+CLA to get the bode-plot of open-loop of closed loop converter. After combining 2 program, I got this problem and I do not know how to solve it. Please help:
Description Resource Path Location Type
output section "Cla1Prog" has both CLA and non-CLA sections; such mixing in the same output section is illegal; could not link section "Cla1Prog:_Cla1Task1:CLA_Tasks.obj" null: output section "Cla1Prog" has both CLA and non-CLA sections; such mixing in the same output section is illegal; could not link section "Cla1Prog:_Cla1Task1:CLA_Tasks.obj" Magnetic_Bearing_Amplifier_ITRI_Protocal_101218 C/C++ Problem
The command file is:
/*==================================================================================*/
/* User specific Linker command file for running from FLASH */
/*==================================================================================*/
/* FILE: F28035_FLASH_HVACI_Sensorless.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/* from FLASH. */
/* */
/* Target: TMS320F28035 */
/* */
/* Version: 1.00 */
/* */
/*----------------------------------------------------------------------------------*/
/* Copyright Texas Instruments ���蕭嚙踝蕭09 */
/*----------------------------------------------------------------------------------*/
/* Revision History: */
/*----------------------------------------------------------------------------------*/
/* Date | Description */
/*----------------------------------------------------------------------------------*/
/* 4/13/09 | Release 1.0 New release. */
/*----------------------------------------------------------------------------------*/
/* Define the memory block start/length for the F28035
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2803x are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0 memory block is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x200
-stack 0x200
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
/* Note that the memory allocation below does not create sections as necessary for
the CLA on the F2803x.
*/
PAGE 0:
RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM (L0-L1)*/
RAML3 : origin = 0x009000, length = 0x001000 /* data RAM (L3) */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3E8000, length = 0x002000 /* on-chip FLASH */
FLASHG : origin = 0x3EA000, length = 0x002000 /* on-chip FLASH */
FLASHF : origin = 0x3EC000, length = 0x002000 /* on-chip FLASH */
FLASHE : origin = 0x3EE000, length = 0x002000 /* on-chip FLASH */
FLASHD : origin = 0x3F0000, length = 0x002000 /* on-chip FLASH */
FLASHC : origin = 0x3F2000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
BOOTROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 :
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
dataRAM : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
RAML2 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */
FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */
CLA_CPU_MSGRAM : origin = 0x001480, length = 0x000080 /* CLA-R/W, CPU-R message RAM */
CPU_CLA_MSGRAM : origin = 0x001500, length = 0x000080 /* CPU-R/W, CLA-R message RAM */
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
Cla1Prog : LOAD = FLASHC, /* Note for running from RAM the load and RUN can be the same */
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_SIZE(_Cla1funcsLoadSize),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
/* Library for IQ math, SFRA and SCI Communication with GUI_SFRA */
{
// --library=rts2800_ml.lib<fs_mpy.obj>
// --library=rts2800_ml.lib<fs_div.obj>
// --library=rts2800_ml.lib<fd_mpy.obj>
// --library=rts2800_ml.lib<fs_add.obj>
--library=SFRA_IQ_Lib.lib<SFRA_IQ_BACKGROUND.obj>
--library=SFRA_IQ_Lib.lib<SFRA_IQ_COLLECT.obj>
--library=SFRA_IQ_Lib.lib<SFRA_IQ_INJECT.obj>
// --library=Solar_Lib_IQ.lib<CNTL_2P2Z_IQ_ASM.obj>
--library=IQmath.lib<IQ16log.obj>
--library=IQmath.lib<IQ16atan2.obj>
--library=IQmath.lib<IQ16mag.obj>
--library=IQmath.lib<IQ16toF.obj>
}
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > RAMM1, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
Cla1Data : > RAML2, PAGE = 1
Mcu1Data : > RAMM1, PAGE = 1
.scratchpad : > RAML2, PAGE = 1
SFRA_IQ_Data : > RAMM1, PAGE = 0
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
Cla1ToCpuMsgRAM : > CLA_CPU_MSGRAM PAGE = 1
CpuToCla1MsgRAM : > CPU_CLA_MSGRAM PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
SFRA_Data : > RAMM1, ALIGN = 64, PAGE=0
RAML0Test : > RAML0, PAGE = 0
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
}
SECTIONS
{
/************* DPLIB Sections C28x ************************/
/* ZeroNet_Section */
ZeroNet_Section : > dataRAM PAGE = 1
}
I just modify the original one by adding the SFRA_data. Please help!!!
Part Number:PROCESSOR-SDK-AM335X
I'd like to run u-boot with the driver model (DM_SPI_FLASH) confgiured in. I want to use the ubifs and load the kernel uImage out of that
I have a few questions...
1) has anyone done this w/ the am335x_evm board?
2) can I use both the CONFIG_SPI_FLASH (legacy interface) and the CONFIG_DM_SPI_FLASH at the same time?
if not how do I do things like use the " sf erase " command? I trield to do this and was not able to compile.
I'm building w/ openembedded poky. using the 2017-09 version of u-boot and we have is25lp512 spi nor roms on our board
otherwise largely same as the am335x_evm
Part Number:AWR1642BOOST
Tool/software: TI-RTOS
Hi all,
I am working on 1642 with CCS and I am wondering how to read the content of RL_LOGV_ARG0()? Does it write the trace somewhere through the uart?
Part Number:DS80PCI810
In my application I need to extend the PCIe bus up to 1M. I would like to use something other than coax if I can. 8 links => 32 cables. VHDCI would seem a decent choice based on the density, intended signalling and so forth. Is this a good choice for a limited range cable between the transmitter and receiver using the 810 on the transmitter side in both directions [install one at the host and one at the target].
Also, any suggestions for CLK and PERST?
I would think PERST could just be buffered since an almost static signal, perhaps with a hysteresis receiver on the target side.
For the clock can we use a buffer and receiver with spread spectrum capability or is there something else TI recommends for this application? Would have been really nice to have that built into this device.
Tool/software: Code Composer Studio
Code composer studio tends to hang and / or crash now and then. That's not a big deal, it's not too common and I'm somewhat used to it. However, when it does so I can't kill the process and therefore can't open another instance in the same workspace. This has started happening once I upgraded to Windows 10 and CCS 8.
Currently my only solution is to reboot, which is terribly inconvenient. Anyone have any ideas?
Part Number:HDC2010
Hi,
In my experiment, it seems writing registers doesn't work right after soft reset (0x0E Reset and DRDY/INT Configuration Register bit 7)
It just shows reset values. However, when I add some delay like 1ms after soft reset and then write something to registers, it works.
Spec doesn't comment about delay for soft reset. Could you tell me how exactly long is the time to complete soft reset?
Thank you,
Won.
Part Number:PTN04050C
Can you provide me with a STEP file of the component? The model's on Digikey website show BGA balls instead of pins.
Part Number:TMS320F28379D
I have read SPRUHM8G TRM and more specifically section 2.13. However, I am not getting the expected result.
Goal: In our use case, I don't want to secure the contents of flash , and RAM. However, I do want that something (JTAG, C2prog.. or any other tool) from outside is unable to access the code.
It is my understanding that ECSL locking would achieve that goal.
So this is what I did:
I programmed a 64 bit pass word at location 0x78028 and left everything else untouched. Using this methodology , I am still able to connect using the JTAG and CCS. However, I do get a message "C28xx_CPU1: Warning: Failed unlocking device (zone 1) after reset." but this seems to have no effect on CCS's ability to connect to the target system.
Can you please elaborate or describe the steps I need to take in order to achieve the above mentioned goal.
Thanks
Part Number:TMS3705
Hi,
Our one of product uses TMS3705A1DRG4, which is EOL. I am looking for replacement part. There are two versions, what I would like to try before PO. Our distributor recommends this forum.
Status of TMS3705EDRQ1 is PREVIEW. Could you tell me estimated release date for it (for sample buy and buy from stock)?
I have tried to get sample TMS3705DDRQ1 from TI. Unfortunately, sample buy url does not work. web page is deadlocked, when I start the process. Is it TI web system failure or I can not order form EMEA regio?
Can I order sample from TI from Hungary?
Best regards,
Attila
Part Number:LAUNCHXL-CC2640R2
Tool/software: Code Composer Studio
I contacted Ti with the following questions. They suggested posting on this (the CCS) forum.
I’ve worked with other programming/microprocessors in the past (more Atmel based).
I downloaded Code Composer Studio (CCS), and was trying to “test-drive” it a little.
It could be inexperience on my part, but CCS didn’t seem to auto-complete well, or have good intellisense. When I type in a function, it seemed to recognize it was a function (would auto insert an open parenthesis), but did not offer help on what arguments should be passed to the function. I also does not seem to have intellisense.
I’m kind-of spoiled using visual studio (and similar IDEs), and was wondering if there is a better IDE. Perhaps I’m not experienced enough with CCS, or there is a better IDE I should try. I’ve used visual-studio based IDEs for other processors, and thought maybe TI had one.
I would like to avoid cloud-based IDEs (I’d like the IDE to run on my local CPU). This is due to the fact sometimes I need to work completely off the network. If needed, I could use a cloud-based IDE, but I think you see the challenges.
The hardware I'm looking at is the LAUNCHXL-CC2640R2. and/or CC2640R2F .
Thanks for any thoughts.