Part Number:LAUNCHXL-F28069M

Tool/software: Code Composer Studio

I tried to load the program Cla_ACos, which is an example ofC2000Ware, into F28069 but the next error appear:

You can notice in the error that appears the file 'F2805x_RAM" instead of 'F2806x_RAM' as it was configured before running the example as it is shown below:

It seems that F28069M has been loocked. I tried to load another project that i was working on and the error still happens. I tried to unlock the F28069 M by using UniFlash but the next error appears:

I am trying to understand how the microcontroller has been locked up with this example since it does not have any section for Password and csm_rsvd in the memory.

I tired with another F28069M board, and it has also been locked trying tu run this example. Anyone has any suggestion on how can i unlocked the two boards? Anybody knows how to run this example properly?

Thanks in advance

Part Number:MSP-EXP430FR2355

Tool/software: Code Composer Studio

Hi everyone,

I am a newbie for interrupt coding. I am using TimerB interrupt for MSP430FR2355 device. Could you please let me know what is wrong in the following code? 

int main(void)
{

WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer

P1DIR |= BIT0; // Set pin with LED1 to output

TB0CCR0 = 100;

TB0CCTL0 = CCIE;

TB0CTL = MC_1|ID_3|TBSSEL_1|TBCLR; //set up timer and start it

}

#pragma vector = TIMER0_B1_VECTOR
__interrupt void TB1_ISR (void)
{
// P1OUT |= BIT0;
while(1) {
volatile unsigned int i; // volatile to prevent optimization

P1OUT ^= 0x01; // Toggle P1.0 using exclusive-OR

i = 10000; // SW Delay
do i--;
while(i != 0);
}

}

From all the references online, it looks like I have all the steps required to use an interrupt. Any help is greatly appreciated. Thank you.

- Ritika

Part Number:ADC128S102

Hi,

We're having an odd problem with the ADC128S102. When we read data off of the converter it flips between 3.3 V and 1.5 V for output high bit. Example logic analyzer capture shown below with a read out of ADC channel 4 (logic analyzer channel 0 is MISO, 1 is SCLK, 2 is MOSI, 3 is CS). I'm at a bit of a loss as to what is going on, we've used this part previously without issue. The current design has VA and VD at 3.3 V, channels 3-8 are tied to 3 V. I had a 39.2 ohm source terminating resistor on the MISO line that I swapped out for a 0 ohm jumper just in case it was somehow loading the output down too much but that had no effect. I have also replaced the ADC once already in case it got damaged or was somehow bad.

Thoughts? Thanks for your help.

Part Number:CC2650

Where can I find the PER Test program for the CC2650?

In the TI rtos, I find a per test program for cc2650, but 802.15.4 mode does not given.

Where can I find it?

Thank you!

Part Number:TMS570LC4357

Hello,

We would like to have more information about N2HET.

As described in the Referendce manual (Figure 23-1.) the N2HET modules can be turn off via the TO bit in the HETGCR register.

But does it mean that all the module is in 'reset state'  (GIO functionality included) ?

Is there a means to deactivate the GIO functionality of the N2HET module at the same time the N2HET 'core' of the N2HET module?

Compared to some other modules, It seems that no choice can be done between N2HET functionality and GIO functionality for N2HET pins.

Best regards,

Christopher

Part Number:MSP430F5342

Hello,

I have recently tried to create a custom BSL for the MSP430F5342 device using the template found in the MSP430 Custom BSL Package.

I used the template for the MSP430F543xA device and changed the memory map to a) adapt it to my device and b) load the BSL code into the BSL section (according to the .map file in the template, the code is loaded into flash starting at 0x10000 instead of the BSL area starting at 0x1000.) When trying to load the sample BSL code into the BSL area, there is not enough space and so an overflow area is needed. To accommodate this, I made the following modifications to lnk_msp430f5342.cmd:

In the MEMORY section:

    /* Get rid of INFO MEM sections
    INFOA                   : origin = 0x1980, length = 0x0080
    INFOB                   : origin = 0x1900, length = 0x0080
    INFOC                   : origin = 0x1880, length = 0x0080
    INFOD                   : origin = 0x1800, length = 0x0080 //Use this area for BSL OverFlow
	*/
    // Added BSL & BSLOF (overflow) section -------------------------------
    BSL						: origin = 0x1042, length = 0x7AE
    BSLOF					: origin = 0x1880, length = 0x200
	// --------------------------------------------------------------------

in the SECTIONS section:

	//Place all output sections into newly defined memory sections
    .text       : {} >> BSL | BSLOF			// Code
    .text:_isr  : {} >> BSL | BSLOF			// ISR code space
    .cinit      : {} > BSL | BSLOF	        // Initialization tables
    .const      : {} >> BSL | BSLOF         // Constant data
    .cio        : {} > RAM                  // C I/O Buffer

    .pinit      : {} > BSL | BSLOF          // C++ Constructor tables
    .binit      : {} > BSL | BSLOF          // Boot-time Initialization tables
    .init_array : {} > BSL | BSLOF          // C++ Constructor tables
    .mspabi.exidx : {} > BSL | BSLOF        // C++ Constructor tables
    .mspabi.extab : {} > BSL | BSLOF        // C++ Constructor tables

#ifdef __TI_COMPILER_VERSION__
  #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} load=BSL | BSLOF, run=RAM, table(BINIT)
  #endif
#endif

The project compiled successfully and I was able to load it into the device. However, after loading it a few more times I am no longer able to access the device and get the message that

"Error connecting to the target:
The Debug Interface to the device has been secured"

I do not understand why this happened. I checked the BSL430_API.c file and the lock key is still 0xFFFFFFFF in my project so the JTAG fuse should not have blown. What is causing this behavior? Is it possible to unlock the device?

Thank you,

svl123

Part Number:TM4C123BH6ZRB

Hi,

I design use I2C queue solution.
1.Can I create second I2C queue? If yes, how can do it?
2.Can I delete old queue message for I2C?
I need high priority from SWI do I2C command.

BR,

JK Wolf

Part Number:OPT9221

Tool/software: TI C/C++ Compiler

Hello TI!

We made our-self board based on your demo-board OPT8241.

My problem is the presence big noise in phase-map for second modulation frequency in de-aliasing mode.

For first frequency it is seem OK.

It is phase-map for first frequency:  (ind_freq_data_en = true, ind_freq_data_sel = false)

It is phase-map for second frequency:   (ind_freq_data_en = true, ind_freq_data_sel = true)

Plain IR image the same scene:

Phase-map for both frequencies:     (ind_freq_data_en = false)

The main registers values are:

{'5C' 'w' '02' '900C42'};
{'5C' 'w' 'B2' '000AAA'};
{'5C' 'w' '03' '101800'};
{'58' 'w' '83' '000026'};

{'58' 'w' '82' '0208D5'};
{'5C' 'w' '4C' '800012'};
{'5C' 'w' '29' '304040'};

{'58' 'w' '0C' '140000'};
{'58' 'w' '0D' '0F0000'};
{'58' 'w' '0F' '00041A'};

The main parameters for depth engine and time generator

ind_freq_data_en = false
use_dealiasing_mode = true
ma = 2
mb = 3
ka = 2
kb = 1
dealiased_ph_mask = 3
phy_test_enable = false
ind_freq_data_sel = false
illum_en_early = false
illum_mod_early = false
intg_duty_cycle = 18
mod_m1 = 20
mod_m_frac1 = 0
mod_m2 = 15
mod_m_frac2 = 0
mod_n1 = 2
mod_n2 = 2
mod_ps1 = 1
mod_ps2 = 0
pix_cnt_max = 133333
sub_frame_cnt_max = 2

Is it normal such noise level for second frequency?

Part Number:DRV8301-69M-KIT

I've just received my kit & powered it up for the first time Monday night. The unit was recognized by my pc & I could see it in the device manager on my computer when I plugged the usb port in. It appeared to work as expected for several hours as I could at least get to the motor to do something in motor characterization portion of the instaspin motion control software. While operating, it appeared as if my device had lost connection & reconnected several times as I could hear the usb audible sounder ping several times. The unit appeared to continue working following this event.

When attempting to start & run the device yesterday night, I received the following error on the last line of the Console Output pane.

"Device Calibration not complete, check if device is unlocked & re-calibrate."

In addition, I cannot see the unit in my device manager before launching the instaspin software but I can here it ping when I plug in the device. In, addition, the yellow light on the onboard 2806 card is lit as well.

Any help resolving this issue would be greatly appreciated. 

I also have a few questions regarding tuning my specific motor for which I believe could be most easily answered with a quick phone call if possible.

Thank you,

Marcus

Part Number:TLC59281

The datasheet shows a graph of output current vs. Rref (Figure 10) with a high value of Rref of 25.2K and output current 2mA.  Can this device be used with higher values of Rref (up to 1Meg?) to get output currents down in the 10's of microamps? If so, what kinds of issues might this create?

Part Number:MSP430F248

Hi Folks,

Can Anyone At Texas Instruments Provide Me With The EOL Statement

for the MSP430F248?

We are engaging in a new subsystem design and we would like to have

TI's Blessing about the longevity of this particular MSP430F248.

An official letter (with TI's Header) to my e-mail address will be very appropriate.

My e-mail address is erubin@Ttetracore.com

Very Respectfully,

Ephi Rubin,

Sr. Hardware Engineer

Part Number:LMZM33606

I am looking for the bxl file and hopefully the 3D step model for this part.

My other concern is that the datasheet and the bxl file for your other parts have Solder Masked Defined pads but when reading your app note SLUA271b-1, TI recommends using Non-Solder Masked Defined pads.

Can you clarify as to which method of solder mask pads to use and, if TI is recommending NSMD pads, please send bxl using NSMD pads?

Thank you.

Tool/software: Linux

Hi,

Hi,

I am using GNU Tools ARM Embedded (arm-none-eabi-gcc.exe with -march=armv7e-m) for my source code together with TI CSL drivers, I am loading the firmware via remoteproc driver in kernel.

• IPU1 is located at 0x90000000 (32MB)
• IPU2 is located at 0x92000000 (32MB)

I want access (read/write) from IPU1 (0x90000000) to the RAM of IPU2 (0x92000000)? Is it possible (I don't want shared RAM)?  If yes, where do I need to configure it (rsc_table, dts-file, linux driver)?

Regards,

Andreas

Part Number:AM3358

Tool/software: Linux

It seems to me that the description of "Building the SDK" need an update. I am looking at the latest 05_01_00_11 description.

Real reason for this is that I am searching for a reason while I am unable to build the SDK.... (another post)

But anyway I get the following errors when trying to install the recommended host tools with:

sudo apt-get install git build-essential python diffstat texinfo gawk chrpath dos2unix wget unzip socat doxygen libc6:i386 libncurses5:i386 libstdc++6:i386 libz1:i386

The following packages have problems:

Package libc6:i386 is not available, but is referred to by another package.
This may mean that the package is missing, has been obsoleted, or
is only available from another source
However the following packages replace it:
libdb1-compat tzdata initscripts

E: Package 'libc6:i386' has no installation candidate
E: Unable to locate package libncurses5:i386
E: Unable to locate package libstdc++6:i386
E: Couldn't find any package by regex 'libstdc++6'
E: Unable to locate package libz1:i386

Part Number:DP83867IS

We are using DP83867ISRGZT for 100 Mbps Ethernet. The MDI A and B channels of the TI PHY are routed to an asymmetric transformer. It does not appear that an asymmetric transformer supports MDI cross over so it is critical that the Tx/Rx assignments are fixed. Does TI agree? Based on Figure 26 in the DP83867ISRGZT datasheet and RJ-45 standard pin definitions, I believe MDI channel A of the PHY is the transmit pair and B is the receive pair. Does TI agree? If I connect the PHY transmit (channel A) to the transformer transmit pins and the PHY receive (channel B) to the transformer receive pins, then I believe I would just need to set PHYCR[6] to 0 to disable MDI crossover. I am not sure what bit 5 should be set to. Based on figure 26, I believe bit 5 should also be set to 0 (MDI configuration). Please advise.

Part Number:BQ21040

Hi,

refer to previous question:

1.

2.

=========================================

The question now is:

1. the battery we used is removeable and with 10K NTC. This means battery and NTC will be removed or inserted together. When battery remove, the #CHG goes high and OUT output voltage 4.2V. We know this is TTDM mode so we add 237KOhm as TS to GND, but sometimes it still happened in few pilot run samples, we have to reduce this resistor to 200KOhm or even 190KOhm then can cover the all samples.

Based on the TS current to calculate the voltage, 237K is enough to prevent IC from entering TTDM, why I have to reduce it to even 190KOhm?

2. I have saw that datasheet have modified the suggest resistor from 250K to 237K, is this because of IC tolerance?

3. due to project is going to mess production, how I can make sure that the 190K is enough for our design?

4. When TTDM successful disable, the OUT goes low while battery removed, but sometimes the #CHG still keep low even TTDM disable and battery removed, I have to touch TS pin by hand or voltage probe than #CHG can goes low. Accordng to the cap inside the voltage probe is 50pF typ., so I add 50pF on TS pin then this issue fixed.

What I want to know is, what make this happened on BQ21040.

Sorry for didn't verify the answer at previous thread due to we still working on it, please help on this, thank you very much!

Best Regards,

C.T.

Part Number:WL1831MOD

>>The Bluetooth stack is fully qualified (QDID 69886 and QDID 69887)

The WL1801MOD datasheet (swrs152m.pdf) lists the above BT SIG QDID's for  TI-BT-STACK_LINUX-ADDON

(as does http://www.ti.com/tool/ti-bt-stack-linux-addon and https://e2e.ti.com/support/wireless-connectivity/wifi/f/968/p/508885/1846167 )

>>WL1835MOD Ubuntu 12.04 QDID 37180
>>WL1837MOD Ubuntu 14.04 QDID 42849

But http://www.ti.com/tool/tibluetoothstack-sdk lists older QDID's. 

The BT SIG links on the old http://processors.wiki.ti.com/index.php/WL18xxMOD_Certificates don't seem to work anymore.  And don't see any BT SIG docs on the newer .zip files in http://www.ti.com/tool/download/WL18XX-REPORTS

Before I file, I just want to make sure I have the correct numbers:
Controller ID: 88827
Host Subsystem ID 37180
Profile Subsystem ID 42849

Or should it be  88827 69886  and 69887?

Part Number:AM3358

Tool/software: Linux

I have installed the latest TI SDK using the steps described in the "Building the SDK". Build tools installed, oe-layer setup run, toolchains installed and set in environment so everything should be OK, But I am getting a strange problem with the build.

I am running "MACHINE=am335x-evm bitbake arago-base-tisdk-image" Many processes seems to complete fine but I always get stuck at the toolchain... already in SetScene it fails (last task missing) and following with a similar error in RunQueue..

I get an PermissionError: [Errno 13], but this does not really make sence... Any help appreciated ;-)

ERROR: external-linaro-toolchain-2017.11-r0.arago36 do_package_setscene: Error executing a python function in exec_python_func() autogenerated:

The stack trace of python calls that resulted in this exception/failure was:
File: 'exec_python_func() autogenerated', lineno: 2, function: <module>
0001:
*** 0002:do_package_setscene(d)
0003:
File: '/home/tm/tisdk/sources/oe-core/meta/classes/package.bbclass', lineno: 2167, function: do_package_setscene
2163:do_package[sstate-lockfile-shared] = "${PACKAGELOCK}"
2164:do_package_setscene[dirs] = "${STAGING_DIR}"
2165:
2166:python do_package_setscene () {
*** 2167: sstate_setscene(d)
2168:}
2169:addtask do_package_setscene
2170:
2171:do_packagedata () {
File: '/home/tm/tisdk/sources/oe-core/meta/classes/sstate.bbclass', lineno: 681, function: sstate_setscene
0677: break
0678:
0679:def sstate_setscene(d):
0680: shared_state = sstate_state_fromvars(d)
*** 0681: accelerate = sstate_installpkg(shared_state, d)
0682: if not accelerate:
0683: bb.fatal("No suitable staging package found")
0684:
0685:python sstate_task_prefunc () {
File: '/home/tm/tisdk/sources/oe-core/meta/classes/sstate.bbclass', lineno: 328, function: sstate_installpkg
0324: for f in (d.getVar('SSTATEPREINSTFUNCS') or '').split() + ['sstate_unpack_package']:
0325: # All hooks should run in the SSTATE_INSTDIR
0326: bb.build.exec_func(f, d, (sstateinst,))
0327:
*** 0328: return sstate_installpkgdir(ss, d)
0329:
0330:def sstate_installpkgdir(ss, d):
0331: import oe.path
0332: import subprocess
File: '/home/tm/tisdk/sources/oe-core/meta/classes/sstate.bbclass', lineno: 359, function: sstate_installpkgdir
0355: src = sstateinst + "/" + plain.replace(workdir, '')
0356: dest = plain
0357: bb.utils.mkdirhier(src)
0358: prepdir(dest)
*** 0359: os.rename(src, dest)
0360:
0361: return True
0362:
0363:python sstate_hardcode_path_unpack () {
Exception: PermissionError: [Errno 13] Permission denied: '/home/tm/tisdk/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/external-linaro-toolchain/2017.11-r0.arago36/sstate-install-package///package' -> '/home/tm/tisdk/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-linux-gnueabi/external-linaro-toolchain/2017.11-r0.arago36/package'

Part Number:MSP430FR6989

Tool/software: Code Composer Studio

I am trying to set-up the code to activate both the horizontal and vertical axis of the joystick on a BoosterPack MKII attached to my MSP430FR6989 Launchpad (by setting ADC signals to the pins controlling the horizontal and vertical axes). With the setup I have now, the code always jumps to the code for ADCMEM1 interrupt (and hence execute MEM1) no matter what. This is how my setup looks right now: Please let me know what is possibly causing the code to always jump to MEM1. 



;P9.2 is horizontal joystick axis A10 is the ADC signal
;P8.7 is vertical joystick axis A4 is the ADC signal


SetupP9 bis.b #BIT2,&P9SEL0 ;
bis.b #BIT2,&P9SEL1 ;
SetupP8 bis.b #BIT7,&P8SEL0 ;
bis.b #BIT7,&P9SEL1 ;


SetupADC12 mov.w #ADC12SHT0_2+ADC12ON+ADC12MSC,&ADC12CTL0 ; 16x
bis.w #ADC12SHP+ADC12CONSEQ_1,&ADC12CTL1 ; ADCCLK = MODOSC; sampling timer
bis.w #ADC12RES_2,&ADC12CTL2 ; 12-bit conversion results
bis.w #ADC12INCH_10,&ADC12MCTL0; A10 ADC input select; Vref=AVCC
bis.w #ADC12INCH_4+ADC12EOS,&ADC12MCTL1
bis.w #ADC12IE1,&ADC12IER0 ; Enable ADC conv complete interrupt

Mainloop mov.w #2500,R15 ; Delay ~5000 cycles between conversions
L1 dec.w R15 ; Decrement R15
jnz L1 ; Delay over?
bis.w #ADC12ENC+ADC12SC,&ADC12CTL0 ; Start sampling/conversion
nop ;
bis.w #LPM0+GIE,SR ; Enter LPM0 w/ interrupt
nop ; for debug
jmp Mainloop ; Again
nop

;-------------------------------------------------------------------------------
ADC12_ISR; ADC12 interrupt service routine
;-------------------------------------------------------------------------------
add.w &ADC12IV,PC ; add offset to PC
reti ; Vector 0: No interrupt
reti ; Vector 2: ADC12MEMx Overflow
reti ; Vector 4: Conversion time overflow
reti ; Vector 6: ADC12HI
reti ; Vector 8: ADC12LO
reti ; Vector 10: ADC12IN
jmp MEM0 ; Vector 12: ADC12MEM0 Interrupt
jmp MEM1 ; Vector 14: ADC12MEM1
reti ; Vector 16: ADC12MEM2
reti ; Vector 18: ADC12MEM3
reti ; Vector 20: ADC12MEM4
reti ; Vector 22: ADC12MEM5
reti ; Vector 24: ADC12MEM6
reti ; Vector 26: ADC12MEM7
reti ; Vector 28: ADC12MEM8
reti ; Vector 30: ADC12MEM9
reti ; Vector 32: ADC12MEM10
reti ; Vector 34: ADC12MEM11
reti ; Vector 36: ADC12MEM12
reti ; Vector 38: ADC12MEM13
reti ; Vector 40: ADC12MEM14
reti ; Vector 42: ADC12MEM15
reti ; Vector 44: ADC12MEM16
reti ; Vector 46: ADC12MEM17
reti ; Vector 48: ADC12MEM18
reti ; Vector 50: ADC12MEM19
reti ; Vector 52: ADC12MEM20
reti ; Vector 54: ADC12MEM21
reti ; Vector 56: ADC12MEM22
reti ; Vector 58: ADC12MEM23
reti ; Vector 60: ADC12MEM24
reti ; Vector 62: ADC12MEM25
reti ; Vector 64: ADC12MEM26
reti ; Vector 66: ADC12MEM27
reti ; Vector 68: ADC12MEM28
reti ; Vector 70: ADC12MEM29
reti ; Vector 72: ADC12MEM30
reti ; Vector 74: ADC12MEM31
reti ; Vector 76: ADC12RDY

MEM1
;Do MEM1 Stuff
bic.w #LPM0,0(SP)
reti

MEM0 
;Do MEM0 stuff
bic.w #LPM0,0(SP)
reti

;------------------------------------------------------------------------------
; Interrupt Vectors
;------------------------------------------------------------------------------
.sect ".reset" ; MSP430 RESET Vector
.short RESET ;
.sect ADC12_VECTOR ; ADC12 Vector
.short ADC12_ISR ;
.end

Part Number:CC2640

I see in section 5.4 Power Consumption Summary, in the 2640 data sheet (swrs176b.pdf), Icore (Core current consumption) is listed at 2.7 uA with Cache retention and listed at 1.2 uA without Cache retention.

How can the Cache be disabled?

Can someone point me to the documents and/or routines showing how to do this?

Regards,

John