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CCS/EVM430-FR6047: MIsmatch between the flowrate calculated and output LPS

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Part Number:EVM430-FR6047

Tool/software: Code Composer Studio

Hello,

I have measured the flow at different flowrates for a 2 inch pipe. I have calibrated using the LPS output from the excel output of USS GUI which appears to be almost linear. I have also manually calculated the (tup - tdown)/(tup*tdown) and compared with the true value. The trend is very erratic (unusable) whereas it has to be the same as LPS. How can we calculate the flow rate by ourselves using the tup, tdown and DelTOF or are we supposed to use only the LPS output.

Regards,

Prudhvi Sagar


CCS/TMS320C6418: Boot sequence debug with CCS 5.5

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Part Number:TMS320C6418

Tool/software: Code Composer Studio

Hi there,

I need to debug what happen at boot time.

I'm using CCS5.5, TMS320C6418 target and developing a custom board.

I need to see the content of the onchip RAM at address 0x00 right after reset and before code located at address 0 is exetued (i.e. I need to see if ROM boot mode is correctly working copying the first 1k of bytes from the external memory into the onchip ram).

How can I debug this with the emulator so that I can be sure that I see what actually happen at boot time?

Thank you

Regards

LM95233: LM95233

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Part Number:LM95233

Hi.

I am using a LM95233 temperature sensor in its default configuration to monitor temperature of ADC12D1000RF IC. However, i am getting a reading of 1 degree Centigrade continuously which doesn't look like the actual temperature of the IC being monitored. Please let me know the correct configuration of the diode select register in this case. Should i configure it for 65 nm or 90 nm process or an MMBT3904 transistor? 

Linux/AM5716: PCIe access error.

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Part Number:AM5716

Tool/software: Linux

We have a custom board with AM5716 connected to PEX9794 and A 10Gb Ethernet switch via the two PCIe interfaces. Sometime during the initialization, we get the error:

omap_l3_noc 44000000.ocp: L3 application error: target 5 mod:1 (unclearable)
omap_l3_noc 44000000.ocp: L3 debug error: target 5 mod:1 (unclearable)

In such cases the PEX9794 is not recognized on the PCIe bus but the other device is there. When probing the non-working case it can be seen that PCIe lane from PEX9794 is still active but the lane from the AM5716 is silent.

I have studied the related questions in the forum and it seems that there should be a power/reset problem but after checking all related signals, I have ran out of options. The current workaround is a complete reset. Is there a way to reset the PCIe bus of AM5716 and do a rescan inside Linux?

Here is the log from a working and non-working case.

Working:

[ 1.417909] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[ 1.418038] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4
[ 1.421029] dra7-pcie 51000000.pcie_rc: GPIO lookup for consumer (null)
[ 1.421041] dra7-pcie 51000000.pcie_rc: using device tree for GPIO lookup
[ 1.421053] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/ocp/axi@0/pcie_rc@51000000[0]'
[ 1.421063] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/ocp/axi@0/pcie_rc@51000000[0]'
[ 1.421072] dra7-pcie 51000000.pcie_rc: using lookup tables for GPIO lookup
[ 1.421082] dra7-pcie 51000000.pcie_rc: lookup for GPIO (null) failed
[ 1.421221] PCI host bridge /ocp/axi@0/pcie_rc@51000000 ranges:
[ 1.421232] No bus range found for /ocp/axi@0/pcie_rc@51000000, using [bus 00-ff]
[ 1.421270] IO 0x20003000..0x20012fff -> 0x00000000
[ 1.421291] MEM 0x20013000..0x2fffffff -> 0x20013000
[ 1.432153] dra7-pcie 51000000.pcie_rc: PCI host bridge to bus 0000:00
[ 1.432167] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 1.432178] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 1.432188] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[ 1.432223] pci 0000:00:00.0: [104c:8888] type 01 class 0x060400
[ 1.432266] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[ 1.432287] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 1.432357] pci 0000:00:00.0: supports D1
[ 1.432366] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 1.432605] PCI: bus0: Fast back to back transfers disabled
[ 1.432784] pci 0000:01:00.0: [11ab:c81d] type 00 class 0x020000
[ 1.432930] pci 0000:01:00.0: reg 0x10: [mem 0xd0000000-0xd00fffff 64bit pref]
[ 1.432987] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x03ffffff 64bit pref]
[ 1.433042] pci 0000:01:00.0: reg 0x20: [mem 0xf0000000-0xf07fffff 64bit pref]
[ 1.433280] pci 0000:01:00.0: supports D1 D2
[ 1.453136] PCI: bus1: Fast back to back transfers disabled
[ 1.453280] pci 0000:00:00.0: BAR 15: assigned [mem 0x22000000-0x27ffffff pref]
[ 1.453292] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
[ 1.453305] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
[ 1.453322] pci 0000:01:00.0: BAR 2: assigned [mem 0x24000000-0x27ffffff 64bit pref]
[ 1.453370] pci 0000:01:00.0: BAR 4: assigned [mem 0x22000000-0x227fffff 64bit pref]
[ 1.453416] pci 0000:01:00.0: BAR 0: assigned [mem 0x22800000-0x228fffff 64bit pref]
[ 1.453461] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 1.453475] pci 0000:00:00.0: bridge window [mem 0x22000000-0x27ffffff pref]
[ 1.453698] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[ 1.453708] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[ 1.453720] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme loaded
[ 1.453843] aer 0000:00:00.0:pcie02: service driver aer loaded
[ 1.454274] dra7-pcie 51800000.pcie: GPIO lookup for consumer (null)
[ 1.454284] dra7-pcie 51800000.pcie: using device tree for GPIO lookup
[ 1.454295] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/ocp/axi@1/pcie@51800000[0]'
[ 1.454305] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/ocp/axi@1/pcie@51800000[0]'
[ 1.454314] dra7-pcie 51800000.pcie: using lookup tables for GPIO lookup
[ 1.454322] dra7-pcie 51800000.pcie: lookup for GPIO (null) failed
[ 1.454433] PCI host bridge /ocp/axi@1/pcie@51800000 ranges:
[ 1.454443] No bus range found for /ocp/axi@1/pcie@51800000, using [bus 00-ff]
[ 1.454475] IO 0x30003000..0x30012fff -> 0x00000000
[ 1.454495] MEM 0x30013000..0x3fffffff -> 0x30013000
[ 1.460279] dra7-pcie 51800000.pcie: PCI host bridge to bus 0001:00
[ 1.460292] pci_bus 0001:00: root bus resource [bus 00-ff]
[ 1.460304] pci_bus 0001:00: root bus resource [io 0x10000-0x1ffff] (bus address [0x0000-0xffff])
[ 1.460314] pci_bus 0001:00: root bus resource [mem 0x30013000-0x3fffffff]
[ 1.460348] pci 0001:00:00.0: [104c:8888] type 01 class 0x060400
[ 1.460388] pci 0001:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[ 1.460409] pci 0001:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 1.460471] pci 0001:00:00.0: supports D1
[ 1.460481] pci 0001:00:00.0: PME# supported from D0 D1 D3hot
[ 1.460711] PCI: bus0: Fast back to back transfers disabled
[ 1.460892] pci 0001:01:00.0: [10b5:9749] type 01 class 0x060400
[ 1.461392] pci 0001:01:00.0: PME# supported from D0 D3hot D3cold
[ 1.473131] PCI: bus1: Fast back to back transfers disabled
[ 1.473149] pci 0001:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 1.473403] pci_bus 0001:02: busn_res: can not insert [bus 02-ff] under [bus 01] (conflicts with (null) [bus 01])
[ 1.473510] pci 0001:02:05.0: [10b5:9749] type 01 class 0x060400
[ 1.474038] pci 0001:02:05.0: PME# supported from D0 D3hot D3cold
[ 1.474472] pci 0001:02:09.0: [10b5:9749] type 01 class 0x060400
[ 1.474999] pci 0001:02:09.0: PME# supported from D0 D3hot D3cold
[ 1.475495] pci 0001:02:19.0: [10b5:9749] type 01 class 0x060400
[ 1.475919] pci 0001:02:19.0: PME# supported from D0 D3hot D3cold
[ 1.476309] PCI: bus2: Fast back to back transfers disabled
[ 1.476326] pci 0001:02:05.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 1.476360] pci 0001:02:09.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 1.476394] pci 0001:02:19.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 1.476655] PCI: bus3: Fast back to back transfers enabled
[ 1.476669] pci_bus 0001:03: busn_res: [bus 03-ff] end is updated to 03
[ 1.476686] pci_bus 0001:03: [bus 03] partially hidden behind bridge 0001:01 [bus 01]
[ 1.476930] PCI: bus4: Fast back to back transfers enabled
[ 1.476941] pci_bus 0001:04: busn_res: [bus 04-ff] end is updated to 04
[ 1.476957] pci_bus 0001:04: [bus 04] partially hidden behind bridge 0001:01 [bus 01]
[ 1.477257] pci 0001:05:00.0: [10b5:1009] type 00 class 0x088000
[ 1.477383] pci 0001:05:00.0: reg 0x10: [mem 0x00000000-0x007fffff]
[ 1.478405] PCI: bus5: Fast back to back transfers disabled
[ 1.478418] pci_bus 0001:05: busn_res: [bus 05-ff] end is updated to 08
[ 1.478435] pci_bus 0001:05: [bus 05-08] partially hidden behind bridge 0001:01 [bus 01]
[ 1.478450] pci_bus 0001:02: busn_res: [bus 02-ff] end is updated to 08
[ 1.478461] pci_bus 0001:02: busn_res: can not insert [bus 02-08] under [bus 01] (conflicts with (null) [bus 01])
[ 1.478477] pci_bus 0001:02: [bus 02-08] partially hidden behind bridge 0001:01 [bus 01]
[ 1.478491] pci 0001:00:00.0: bridge has subordinate 01 but max busn 08
[ 1.479028] pci 0001:00:00.0: BAR 14: assigned [mem 0x30800000-0x30ffffff]
[ 1.479040] pci 0001:00:00.0: BAR 0: assigned [mem 0x30100000-0x301fffff]
[ 1.479053] pci 0001:00:00.0: BAR 1: assigned [mem 0x30020000-0x3002ffff]
[ 1.479068] pci 0001:01:00.0: BAR 14: assigned [mem 0x30800000-0x30ffffff]
[ 1.479080] pci 0001:02:19.0: BAR 14: assigned [mem 0x30800000-0x30ffffff]
[ 1.479089] pci 0001:02:05.0: PCI bridge to [bus 03]
[ 1.479142] pci 0001:02:09.0: PCI bridge to [bus 04]
[ 1.479198] pci 0001:05:00.0: BAR 0: assigned [mem 0x30800000-0x30ffffff]
[ 1.479218] pci 0001:02:19.0: PCI bridge to [bus 05-08]
[ 1.479241] pci 0001:02:19.0: bridge window [mem 0x30800000-0x30ffffff]
[ 1.479279] pci 0001:01:00.0: PCI bridge to [bus 02-08]
[ 1.479302] pci 0001:01:00.0: bridge window [mem 0x30800000-0x30ffffff]
[ 1.479338] pci 0001:00:00.0: PCI bridge to [bus 01]
[ 1.479349] pci 0001:00:00.0: bridge window [mem 0x30800000-0x30ffffff]
[ 1.479560] pcieport 0001:00:00.0: Signaling PME through PCIe PME interrupt
[ 1.479569] pci 0001:01:00.0: Signaling PME through PCIe PME interrupt
[ 1.479577] pci 0001:02:05.0: Signaling PME through PCIe PME interrupt
[ 1.479584] pci 0001:02:09.0: Signaling PME through PCIe PME interrupt
[ 1.479591] pci 0001:02:19.0: Signaling PME through PCIe PME interrupt
[ 1.479598] pci 0001:05:00.0: Signaling PME through PCIe PME interrupt
[ 1.479608] pcie_pme 0001:00:00.0:pcie01: service driver pcie_pme loaded
[ 1.479799] aer 0001:00:00.0:pcie02: service driver aer loaded
[ 1.479890] pcieport 0001:01:00.0: enabling device (0140 -> 0142)
[ 1.481866] pcieport 0001:02:19.0: enabling device (0140 -> 0142)

Non-working:

[ 1.417543] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[ 1.417674] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4
[ 1.420734] dra7-pcie 51000000.pcie_rc: GPIO lookup for consumer (null)
[ 1.420746] dra7-pcie 51000000.pcie_rc: using device tree for GPIO lookup
[ 1.420758] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/ocp/axi@0/pcie_rc@51000000[0]'
[ 1.420768] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/ocp/axi@0/pcie_rc@51000000[0]'
[ 1.420777] dra7-pcie 51000000.pcie_rc: using lookup tables for GPIO lookup
[ 1.420787] dra7-pcie 51000000.pcie_rc: lookup for GPIO (null) failed
[ 1.420924] PCI host bridge /ocp/axi@0/pcie_rc@51000000 ranges:
[ 1.420936] No bus range found for /ocp/axi@0/pcie_rc@51000000, using [bus 00-ff]
[ 1.420974] IO 0x20003000..0x20012fff -> 0x00000000
[ 1.420995] MEM 0x20013000..0x2fffffff -> 0x20013000
[ 1.432232] dra7-pcie 51000000.pcie_rc: PCI host bridge to bus 0000:00
[ 1.432247] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 1.432258] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 1.432267] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[ 1.432302] pci 0000:00:00.0: [104c:8888] type 01 class 0x060400
[ 1.432344] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[ 1.432366] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 1.432434] pci 0000:00:00.0: supports D1
[ 1.432444] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 1.432683] PCI: bus0: Fast back to back transfers disabled
[ 1.432862] pci 0000:01:00.0: [11ab:c81d] type 00 class 0x020000
[ 1.433005] pci 0000:01:00.0: reg 0x10: [mem 0xd0000000-0xd00fffff 64bit pref]
[ 1.433116] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x03ffffff 64bit pref]
[ 1.433173] pci 0000:01:00.0: reg 0x20: [mem 0xf0000000-0xf07fffff 64bit pref]
[ 1.433362] pci 0000:01:00.0: supports D1 D2
[ 1.453129] PCI: bus1: Fast back to back transfers disabled
[ 1.453273] pci 0000:00:00.0: BAR 15: assigned [mem 0x22000000-0x27ffffff pref]
[ 1.453285] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
[ 1.453299] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
[ 1.453316] pci 0000:01:00.0: BAR 2: assigned [mem 0x24000000-0x27ffffff 64bit pref]
[ 1.453364] pci 0000:01:00.0: BAR 4: assigned [mem 0x22000000-0x227fffff 64bit pref]
[ 1.453410] pci 0000:01:00.0: BAR 0: assigned [mem 0x22800000-0x228fffff 64bit pref]
[ 1.453455] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 1.453469] pci 0000:00:00.0: bridge window [mem 0x22000000-0x27ffffff pref]
[ 1.453693] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[ 1.453703] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[ 1.453714] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme loaded
[ 1.453837] aer 0000:00:00.0:pcie02: service driver aer loaded
[ 1.454268] dra7-pcie 51800000.pcie: GPIO lookup for consumer (null)
[ 1.454279] dra7-pcie 51800000.pcie: using device tree for GPIO lookup
[ 1.454289] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/ocp/axi@1/pcie@51800000[0]'
[ 1.454298] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/ocp/axi@1/pcie@51800000[0]'
[ 1.454306] dra7-pcie 51800000.pcie: using lookup tables for GPIO lookup
[ 1.454315] dra7-pcie 51800000.pcie: lookup for GPIO (null) failed
[ 1.454427] PCI host bridge /ocp/axi@1/pcie@51800000 ranges:
[ 1.454438] No bus range found for /ocp/axi@1/pcie@51800000, using [bus 00-ff]
[ 1.454470] IO 0x30003000..0x30012fff -> 0x00000000
[ 1.454491] MEM 0x30013000..0x3fffffff -> 0x30013000
[ 1.460807] dra7-pcie 51800000.pcie: PCI host bridge to bus 0001:00
[ 1.460820] pci_bus 0001:00: root bus resource [bus 00-ff]
[ 1.460832] pci_bus 0001:00: root bus resource [io 0x10000-0x1ffff] (bus address [0x0000-0xffff])
[ 1.460842] pci_bus 0001:00: root bus resource [mem 0x30013000-0x3fffffff]
[ 1.460877] pci 0001:00:00.0: [104c:8888] type 01 class 0x060400
[ 1.460920] pci 0001:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[ 1.460941] pci 0001:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 1.461001] pci 0001:00:00.0: supports D1
[ 1.461010] pci 0001:00:00.0: PME# supported from D0 D1 D3hot
[ 1.461242] PCI: bus0: Fast back to back transfers disabled
[ 1.485829] omap_l3_noc 44000000.ocp: L3 application error: target 5 mod:1 (unclearable)
[ 1.485847] omap_l3_noc 44000000.ocp: L3 debug error: target 5 mod:1 (unclearable)
[ 1.485859] PCI: bus1: Fast back to back transfers enabled
[ 1.485974] PCI: bus2: Fast back to back transfers enabled
[ 1.485987] pci_bus 0001:02: busn_res: [bus 02-ff] end is updated to 02
[ 1.486129] pci 0001:00:00.0: BAR 0: assigned [mem 0x30100000-0x301fffff]
[ 1.486144] pci 0001:00:00.0: BAR 1: assigned [mem 0x30020000-0x3002ffff]
[ 1.486156] pci 0001:00:00.0: PCI bridge to [bus 02]
[ 1.486215] pcieport 0001:00:00.0: enabling device (0000 -> 0002)
[ 1.486392] pcieport 0001:00:00.0: Signaling PME through PCIe PME interrupt
[ 1.486405] pcie_pme 0001:00:00.0:pcie01: service driver pcie_pme loaded
[ 1.486521] aer 0001:00:00.0:pcie02: service driver aer loaded

Thanks,

Meysam

NO LOAD CURRENT , chip be damaged with PH shorting to GND when the TPS54335A is kept being enabled?

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Part Number:TPS54335A

When our product is in sleep mode, the  waveform of PH pin  is showed below. please help confirm if the status is permitted.

Linux/CC2650: BOOSTXL- CC2650MA

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Part Number:CC2650

Tool/software: Linux

Hello , we are using BOOSTXL- CC2650MA which is CC2650 Module Boostpack for our project . We are interfacing this module through UART interface with i.MX8 CPU EVK. We are using Yocto Linux build version 4.9.xx which does have UART driver.

We got CONTIKI-MASTER software package we got from the website but it does not have linux support.

So please support us to understand how we can interface this module in Linux environment.

TPS22942: Vout not working properly

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Part Number:TPS22942

Hi,

I am pursuing TPS22942 and made a circuitry (shown below) for powering on/off the supply source to a RF module. RF module takes 45mA approx. VCC_3V is the input source and VCC_3V_RF is the output. While I am making RF_POWER_ONOFF='0', VCC_3V_RF is going to 3V. However it is going to 2.3V approx while RF_POWER_ONOFF='1'. Below is the waveform. I am fine with the RF_OCn behavior as shown in below waveform. Also I have measured that VIN voltage is steadily 3V at all times (no spikes/dips).

I checked the behavior of RF module with another circuitry that has a switch. Basically I used a voltage regulator TPS62740, and controlled its CTRL pin for powering on/off the supply source to RF module. The LOAD output from this regulator is properly powering on to 3V and powering off to 0V. So, there does not seem to be any issue with the RF module.

I have also checked the above TPS22942 circuitry behavior without any RF module connection. Then, the switch seems to behave as intended. VOUT is going to 0V when it is switched off.

I don't think the above abnormal behavior of TPS22942 is due to output/input capacitance values, because the output remains at 2.3V continuously. Not sure if I am missing something in its behavior. Kindly suggest why TPS22942 is behaving as above, and how can its VOUT behave appropriately. Kindly let me know if you need any further info from my side.

Thanks & Regards,

Vikas Chandra Rao.

RTOS/CC1310: How to recover RF driver when RF_runCmd() lockup?

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Part Number:CC1310

Tool/software: TI-RTOS

Hi, 

these days, during testing CC1310 Tx/Rx, (we use the lastest SDK simplelink_cc13x0_sdk_2_30_00_20), during some heavy traffic, we found that CC1310 can hangup randomly.

after days tracking, we found that in some scenario, CC1310 can lockup in line

RF_runCmd(RadioIF_Rf_Handle, (RF_Op*)RF_cmdPropRadioDivSetup, RF_PriorityNormal, NULL, 0)
a further trace can found it locked on the line in RF_runCmd(....) in RFCC26XX_singleMode.c
 return RF_pendCmd(h, ch, (RF_EventCmdAborted | RF_EventCmdStopped | RF_EventCmdCancelled));
when browse the code : we found this line in RF_pendCmd(... ):
SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER);
this line just wait forever. so when error happened, it never quit.
so I tried to add a timeout onto it: 

/* Wait for semaphore */
rf_state_good = 1;

_state = SemaphoreP_pend(&h->state.semSync, 100*100UL);

if(_state != SemaphoreP_OK)
{
 rf_state_good = 0;

}

after this change, we can detect the timeout condition, and it can quit the RF_pendCmd(...), but after that, in our main task , we catch the rf_state_good  status, and do recover RF task by using 
RF_close(RadioIF_Rf_Handle);
....
RF_open(...)
but it again failed @ RF_close(..), (it can lock up in RF_close again), and the RF drvier can't recover anymore.
the only way is to do a software reset to recover the system to bring the RF back to work.
so I want to know: when detect a RF error, is there a way to call some routine to just re-power up the RF driver to let the RF driver back to work regardless the RF previous status?
B/R,
Shaowei

 


ADS8320: charge bucket configuration

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Part Number:ADS8320

Hello,

I'm currently using the ADS8320 in one of my designs. However, I have a question about the configuration of the external RC filter.
Does this have to be a differential filter, like  stated in the layout example as the first figure. Or should this rather be a single ended version with -In connected straight to GND sense, e.g. second picture?

Thanks in advance,

Sven

Linux/BQ27542-G1: capacity will not rise up after a high current discharging.

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Part Number:BQ27542-G1

Tool/software: Linux

Hi ,Ti team

     We try to discharging a phone battery(3000mAh) with a 1.5A current. battery capacity will drop to 0% and trigger a phone shutting down. After charging battery again for a long time(about one hour), the capacity is always reported as 1%, and FCC dropped to just 300mAh. After charging FULL again,  the FCC changed back to 2980mAh. Can you please tell us what happened?

TMS320C5535: TMS320C5535

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Part Number:TMS320C5535

Hi...

Which Bluetooth module or evaluation board is best suited for this DSP to use in the project?

LM337L: Ripple rejection performance

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Part Number:LM337L

Hi,

a costumer of mine would like to know how the ripple rejection of the LM337L perofrmes over frequency. In the datasheet of the LM337-N are plots that show this info. Do we have such plots also for the LM337L or is it safe to assume, that the performance is equal?

Thanks!

TMS570LS3137: Port Direction registers are overwritten during initialization of PWM and ICU

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Part Number:TMS570LS3137

In AUTOSAR_MCAL_TMS570LSx-05.30.00, Direction register is overwritten in below scenarios

Scenario1

The Direction Register of N2HET1 having UserConfiguration from Port_Init is overwritten after PWM_Init

Details:
In the Port_Config for PortPinN2Het1_25
InitialPortMode = DIO
Direction = OUTPUT
For PIN_V5_37
Pin_Mux = ALT_1
DIR Regsiter values after Port_Init -- > 0x02400202

After the Call to PWM_init, it is automatically set to Input.
DIR register after PWM_Init is --> 0x0000FFFF

I see the below code extract (Pwm_Het_Init) doing this.
HET_PRY(RegBaseAddress) = 0x0000FFFFU; /* Channels 0 to 15 are priority level 1, 16 to 31 priority level 2 */
HET_PFR(RegBaseAddress) = 0x00000700U;
HET_CGR(RegBaseAddress) = 0x00030001U;
HET_PDR(RegBaseAddress) = 0x00U;
HET_PULLDIS(RegBaseAddress) = 0xFFFF0000U;
HET_PSL(RegBaseAddress) = 0xFFFF0000U;
HET_DIR(RegBaseAddress) = 0x0000FFFFU;

• Please explain the reason for hardcoding the direction register thereby ignoring the Port user configuration. From my understanding the registers should be written from the user configured values and not some hardcoded/magic numbers.

It is not allowed as per AUTOSAR to overwrite the user configuration.

 Scenario 2

Same as  PWM_Init, the Icu_Init also changes or overwrites the DIR register. It is not acceptable to use the Port_SetDirection() as a workaround as the Direction was already set in the Port module. Please work on removing this overwriting of the registers in the ICU_Init too.

Additional Query

What is the significance of hardcoding below registers for PWM and ICU?

HET_PRY(RegBaseAddress) = 0x0000FFFFU; /* Channels 0 to 15 are priority level 1, 16 to 31 priority level 2 */
HET_PFR(RegBaseAddress) = 0x00000700U;
HET_CGR(RegBaseAddress) = 0x00030001U;
HET_PDR(RegBaseAddress) = 0x00U;
HET_PULLDIS(RegBaseAddress) = 0xFFFF0000U;
HET_PSL(RegBaseAddress) = 0xFFFF0000U;

MSP430FR5994: Comparator (COMP_E) interrupt triggers at startup

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Part Number:MSP430FR5994

Hi,

I have the COMP_E analog comparator module setup as follows:

    //Initialize the Comparator E module
    /*
     * Base Address of Comparator E,
     * Pin CE13 to Positive(+) Terminal
     * Reference Voltage to Negative(-) Terminal
     * Normal Power Mode
     * Output Filter On with minimal delay
     * Non-Inverted Output Polarity
     */
    Comp_E_initParam param = {0};
    param.posTerminalInput = COMP_E_INPUT5;
    param.negTerminalInput = COMP_E_VREF;
    param.outputFilterEnableAndDelayLevel = COMP_E_FILTEROUTPUT_DLYLVL4;
    param.invertedOutputPolarity = COMP_E_NORMALOUTPUTPOLARITY;
    Comp_E_init(COMP_E_BASE, &param);

    //Set the reference voltage that is being supplied to the (-) terminal
    /*
     * Base Address of Comparator E,
     * Reference Voltage of 2.0 V,
     * Lower Limit of 2.0*(22/32) = 1.375V,
     * Upper Limit of 2.0*(22/32) = 1.375V
     */
    Comp_E_setReferenceVoltage(COMP_E_BASE,
        COMP_E_VREFBASE2_0V,
        22,
        22
        );

    //Enable COMP_E Interrupt on default rising edge for CEIFG
    Comp_E_setInterruptEdgeDirection(COMP_E_BASE, COMP_E_RISINGEDGE);
    // Clear any erroneous interrupts
    Comp_E_clearInterrupt(COMP_E_BASE, (COMP_E_OUTPUT_INTERRUPT_FLAG + COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY));

    //Enable Interrupts
    /*
     * Base Address of Comparator E,
     * Enable COMPE Interrupt on default rising edge for CEIFG
     */
    Comp_E_clearInterrupt(COMP_E_BASE, COMP_E_OUTPUT_INTERRUPT_FLAG);


    Comp_E_enableInterrupt(COMP_E_BASE, COMP_E_OUTPUT_INTERRUPT);

    //Allow power to Comparator module
    Comp_E_enable(COMP_E_BASE);

    __delay_cycles(400);           // delay for the reference to settle

    __enable_interrupt();



//******************************************************************************
//
//This is the COMP_E_VECTOR interrupt vector service routine.
//
//******************************************************************************
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=COMP_E_VECTOR
__interrupt
#elif defined(__GNUC__)
__attribute__((interrupt(COMP_E_VECTOR)))
#endif
void COMP_E_ISR(void){
    if (enableVM){
        //Toggle the edge at which an interrupt is generated
        Comp_E_toggleInterruptEdgeDirection(COMP_E_BASE);

        //Clear Interrupt flag
        Comp_E_clearInterrupt(COMP_E_BASE, COMP_E_OUTPUT_INTERRUPT_FLAG);

        //Toggle P1.0 output pin.
        GPIO_toggleOutputOnPin( GPIO_PORT_P1, GPIO_PIN0 );
    }
}

The code toggles LED P1.0 when input voltage goes above or below the reference voltage (1.375V). Input is from pin P1.5. When I toggle the input voltage the interrupt fires as expected.

When the system starts up the LED lights up, But i've put the LED to LOW at startup (before the comparator is initialized) like so:

// P1.0 (LED)
GPIO_setAsOutputPin(GPIO_PORT_P1, GPIO_PIN0);
GPIO_setOutputLowOnPin(GPIO_PORT_P1,GPIO_PIN0);

So I suspect the COMP_E interrupt is firing immediately when enabled. Why is this ? have I configured it incorrectly ?

thanks

TPS25944L: Two level efuse

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Part Number:TPS25944L

Hi, 

I have an application that can be either powered from USB or external power adapter. Depending on if there is external power or not i would like to increase the efuse current limit. 

I have made the following (simplified) circuit:

A comparator is used to detect if external power adapter is preset, which in turn enables Q1. 

I know this is not the typical application and its also likely to be the reason for the odd behavior i get from this circuit because of this, which is the following:

1) The default condition is USB powered, which uses only RB to set ILIM.

2) If external power is connected RA is put in parallel to RB changing the limit (increasing ILIM). which works fine.

3) If than the load is adjusted to somewhere in the new higher limit range, and external power adapter is removed. ILIM is changed back to the lower limit with only RB. In this situation the efuse seems to trip as expected (disable output), but the fault pin did not change state to fault condition (It seems like there is only rising edge flank current detection to generate the over-current fault condition?).

A solution would be to give a reset pulse in case external power is removed, but this also disconnects the load for the pulse duration which in case of a "light load which could be USB powered" is undesired. 

Does anyone know if there's a easy workaround for this issue?

Regards,

Ivo


LP8733-Q1: Can these materials be set the output voltage according to the customer requirements?

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Part Number:LP8733-Q1

Dears:

Customer wants to know if their project is in MP state, can these materials be set the output voltage according to the customer requirements?

What is the process? 

Compiler/CC2650: cc2650

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Part Number:CC2650

Tool/software: TI C/C++ Compiler

hey i am using IAR (8.32.1 version) and ble stack 2_02_02_25   , ble stack 2_02_01_18

if can't able to download application i am getting following error please help to to solve it.

for above both stack i am getting same error as shown in below.

Building configuration: cc2650stk_app - FlashROM 
Updating build tree... 
Performing Pre-Build Action 
Error while running "C:\ti\xdctools_3_32_00_06_core/xs" --xdcpath="C:\ti\tirtos_cc13xx_cc26xx_2_21_01_08\products\ 
tidrivers_cc13xx_cc26xx_2_21_01_01\packages;C:\ti\tirtos_cc13xx_cc26xx_2_21_01_08\products\bios_6_46_01_38\ 
packages" iar.tools.configuro -c "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm" --cc "C:\Program 
Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\bin\iccarm.exe" --device "CC2650F128" --compileOptions 
"dummy.c -D CC2650STK -D CC26XX -D Display_DISABLE_ALL -D EXCLUDE_AUDIO -D 
EXCLUDE_FACTORY_RESET -D EXCLUDE_OAD -D GAPROLE_TASK_STACK_SIZE=440 -D 
GATT_TI_UUID_128_BIT -D HEAPMGR_SIZE=0 -D ICALL_MAX_NUM_ENTITIES=11 -D ICALL_MAX_NUM_TASKS=8 
-D POWER_SAVING -D USE_ICALL -D xdc_runtime_Assert_DISABLE_ALL -D xdc_runtime_Log_DISABLE_ALL 
--diag_suppress Pa050 -o C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\FlashROM\Obj 
--debug --endian=little --cpu=Cortex-M3 -f C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\ 
..\..\..\..\src/config/build_components.opt -f C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\ 
stack\build_config.opt -f C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\config\configPkg\ 
compiler.opt.defs -f C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\config\ 
iar_boundary.bdef -e --fpu=None --dlib_config \"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\inc\ 
c\DLib_Config_Normal.h\" -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\ 
src/controller/cc26xx/inc\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src/inc\ 
-I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src/common/cc26xx\ -I C:\ti\ 
simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src/examples/sensortag/cc26xx/app\ -I 
C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src/icall/inc\ -I C:\ti\simplelink\ 
ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src/inc\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\ 
examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src/profiles/batt/cc26xx\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\ 
examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src/profiles/dev_info\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\ 
cc2650stk\sensortag\iar\app\..\..\..\..\..\src/profiles/hid_dev/cc26xx\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\ 
cc2650stk\sensortag\iar\app\..\..\..\..\..\src/profiles/keys\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk
sensortag\iar\app\..\..\..\..\..\src/profiles/roles\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\ 
app\..\..\..\..\..\src/profiles/roles/cc26xx\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\ 
..\..\..\..\src/profiles/sensor_profile/cc26xx\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\ 
..\..\..\..\..\src/target\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src\ 
components/hal/src/inc\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\..\..\..\src\ 
components/hal/src/target/_common\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\ 
..\..\..\src\components/hal/src/target/_common/cc26xx\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk
sensortag\iar\app\..\..\..\..\..\src\components/heapmgr\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk
sensortag\iar\app\..\..\..\..\..\src\components/icall/src\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk
sensortag\iar\app\..\..\..\..\..\src\components/icall/src/inc\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk
sensortag\iar\app\..\..\..\..\..\src\components/osal/src/inc\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk
sensortag\iar\app\..\..\..\..\..\src\components/services/src/saddr\ -I C:\ti\simplelink\ble_sdk_2_02_02_25\examples\ 
cc2650stk\sensortag\iar\app\..\..\..\..\..\src\components/services/src/sdata\ -I C:\ti\tirtos_cc13xx_cc26xx_2_21_01_08\ 
products\cc26xxware_2_24_03_17272\ -I C:\ti\tirtos_cc13xx_cc26xx_2_21_01_08\products\ 
tidrivers_cc13xx_cc26xx_2_21_01_01\packages\ -I C:\ti\tirtos_cc13xx_cc26xx_2_21_01_08\products\ 
tidrivers_cc13xx_cc26xx_2_21_01_01\packages/ti/mw/extflash\ -I C:\ti\tirtos_cc13xx_cc26xx_2_21_01_08\products\ 
tidrivers_cc13xx_cc26xx_2_21_01_01\packages/ti/mw/sensors\ -I C:\ti\tirtos_cc13xx_cc26xx_2_21_01_08\products\ 
tidrivers_cc13xx_cc26xx_2_21_01_01\packages/ti/mw/sensortag\ -Ohz" --linkOptions "--no_out_extension -o C:\ti\ 
simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\FlashROM\Exe\sensortag_cc2650stk_app.out 
--map C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\FlashROM\List\ 
sensortag_cc2650stk_app.map --config C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk\sensortag\iar\app\..\..\ 
..\..\..\src/common/cc26xx/iar/cc26xx_app.icf --keep __vector_table -f C:\ti\simplelink\ble_sdk_2_02_02_25\examples\ 
cc2650stk\sensortag\iar\app\..\config\configPkg\linker.cmd -f C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk
sensortag\iar\app\..\config\iar_boundary.xcl --semihosting C:\ti\simplelink\ble_sdk_2_02_02_25\examples\cc2650stk
sensortag\iar\app\..\..\..\..\..\src\rom\common_rom_releases\03282014\common_rom.symbols C:\ti\ 
tirtos_cc13xx_cc26xx_2_21_01_08\products\cc26xxware_2_24_03_17272\driverlib\bin\iar\driverlib.lib --entry 
__iar_program_start --vfe --text_out locale" --profile release --projFile "C:\ti\simplelink\ble_sdk_2_02_02_25\examples\ 
cc2650stk\sensortag\iar\app\cc2650stk_app.ewp" 

Total number of errors: 1 
Total number of warnings: 0

 thanks and regards 

santhosh

TPS2546: STATUS behavior

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Part Number:TPS2546

Hi,

I have some STATUS pin related questions when I test our EVM with input from DC power supply and output connected to a current load.

When CTL1/CTL2/CTL3/ILIM_SEL= “0111”

    1. If the current load is below ILD as below, STATUS would stay high, is it expected behavior?
    2. If the current load is above ILD, STATUS become low after the current load is enabled.  But, 2 seconds later Vout becomes low for 2 seconds and back to high level.  Is it normal?  Why we have such behavior at Vout?  ( I don't see such Vout behavior when CTL1/CTL2/CTL3/ILIM_SEL= “1111”, why?)
    3. STATUS become high around 3 seconds after current is removed from the board, is it normal?  Is 3sec the "Load detect reset time" in the table as below?
    4. When a current load higher than ilim_hi is connected, Vout will become low, but try to be enabled again shortly each 2.2 seconds.  Why it's 2.2 seconds?  Do we define it in datasheet?  I found this period is around 400ms when CTL1/CTL2/CTL3/ILIM_SEL= “1111”, why the timing is different?

Thanks

Antony

MSP430G2544: BGA package, layout/design guidelines

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Part Number:MSP430G2544

Team,

we will use MSP430 in BGA49 package YYF (R-XBGA-N49). I wonder what is recommended landing pattern for it.

I have found document www.ti.com/.../spraav1b.pdf, which describes recommended PCB Design
Guidelines for 0.4mm Package-On-Package for OMAP350 processors. Is it valid for smaller BGA49 of MSP430GxxxYYF, too?

Namely what about solder-mask-defined pads vs. non-solder-mask-defined pads design. Please advise.

Thanks for your help.

TMS570LS3137: NHET pin configuration limitation for PWM and ICU drivers

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Part Number:TMS570LS3137

In AUTOSAR_MCAL_TMS570LSx-05.30.00, we are not able to configure PWM for N2HET[16] and above. Also, ICU configuration is not allowed from pins N2HET[0] - [15]. 

Why is such limitations?

How do we meet Customer requirements?

 

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