Part Number:CC2640R2F

Tool/software: TI-RTOS

Hello,

I am getting the below linker error when i build my code. Actually I have ported my code from cc2640 to cc2640r2, and it was properly working. Now I have added the OTA module to my code, and during linking I am getting this error. Please help me find a solution for this.

Error[Lp011]: section placement failed
            unable to allocate space for sections/blocks with a total estimated minimum size of 0x2060 bytes (max align 0x8) in <[0x11000000-0x11002000]> (total uncommitted space 0x2001).

Error[Lp017]: the address of "devInfoSystemId (devinfoservice.o)" was needed when computing compressed initializers for section .data (devinfoservice.o #43), but that address hasn't been  
set yet, since the size of the compressed initializers are needed in order to set it

Error[Lp017]: the address of "ti_sysbios_family_arm_m3_Hwi_Module_State_0_excActive__A" was needed when computing compressed initializers for section  
.data_ti_sysbios_family_arm_m3_Hwi_Module__state__V (app_ble_prm3.orm3 #156), but that address hasn't been set yet, since the size of the compressed initializers are needed in order to  
set it

Part Number:DP83822IF

Hi Ti experts,

      Previous ,we have used DP83822IF in100M-TX mode , the function is OK.  now , we are using DP83822IF in 100M-FX mode,  there is a packet loss in first few packet,  then I read the link status of register 0x0001(bit 2), 0x08 is the PHY address of one port, before I read it,the fiber connection is OK, the first value is 0x7849, that is to say, the link is not eatablished, but after the first time I read it, the link status is OK ,

I don't know why the first link status is abnormal?  thanks for your help

.

Part Number:TM4C123BH6ZRB

Hello,

TM4C123BH6ZRB datasheet intro of BOOTCFG says: '...by using any GPIO signal from Ports A-Q as configured by the bits in this Register.'

But in register description "PORT" of BOOTCFG Register only 3 bits are intended!

Am I able to use port "Q" for BOOTCFG function? I'm afraid not...

Thanks in advance,

Tobi

Part Number:TDA3XEVM

Hi team,

I find an application note named "Interfacing Between LVPECL, LVDS and CML",http://www.ti.com/analog/docs/litabsmultiplefilelist.tsp?literatureNumber=scaa056&docCategoryId=1&familyId=346&keyMatch=SCAA056&tisearch=Search-EN-Everything

I find LVPECL to CML interface using AC coupling, the attentuation factor should be CML/LVPECL swing. so the example caluation that I shown below makes mistake to get 0.68 for CML400mV/LVPECL 750mV? Is that a typing mistake or my caluation mistake?

thanks for your clarification!

Part Number:TMS320F280049

Hi expert,

We are sampling HV DC through voltage divider into ADCs. We met some problem that the divided voltage signal is clamped on some channels (can not go up than 2.2V when increase HV DC, reference is 3.3V) where these pins are connected to multiple ADC inputs such as pin 36 in 100 pin package. But this problem will not happen on pins connected with only one ADC input such as pin 38 in 100 pin package.

We already tested these ADC channels with signal source, everything is fine with a strong source. So we would like to know the reason behind this phenomenon. Did these pins get different input impedence?

We'd like to do some test by directly route signal (divided HV DC) into ADC through PAG_OF pin with ADC input disabled. Is that possible?

Thanks

Sheldon

Part Number:ADC3424

Hi Team,

We are penetrate our ADC3424 in my customer in new project. Also we finally choose LMH6518 to drive ADC3424. Now customer plan to do schematic, so Can some expert help to share some reference schematic or guidance to show how to use LMH6518 to drive ADC3424, this will help customer to move ahead more smoothly. Thanks for the support!

Best regards,

Sulyn 

Part Number:AM5728

Tool/software: Linux

Hi,

I'm developing over IDK am5728 with PROCESSOR-SDK-LINUX-AM57X version v05.00 and PROCESSOR-SDK-RTOS-AM57X version v05.00.

I'm using the jailhouse hypervisor and I'm able to run linux on core 0 and on core 1 the jailhouse inmate demo processor_sdk_rtos_am57xx_5_00_00_15/demos/jailhouse-inmate/rtos/icss_emac

Now I'm trying to create inter cell communication. I need the cores to be able to send interrupts to one another.

I'm using the uio-ivshmem module from https://github.com/henning-schild-work/ivshmem-guest-code

To simplify things, first I'm trying to send an interrupt from a baremetal inmate to the root-cell Linux. Later I will try with RTOS inmate.

Once I have that working I will need the RTOS inmate to receive an interrupt from the Linux root cell.

In the dts file some GIC inputs are reserved for the inmate:

                pruss2_eth {
                        status = "disabled";
                };

in the root cell I set
.vpci_irq_base = 100 - 32

and in the inmate cell
.vpci_irq_base = 134 - 32,

pci and uio_ivshmem init seem fine

[   45.928817] OF: PCI: host bridge /vpci@0 ranges:
[   45.933482] OF: PCI:   MEM 0x30100000..0x30101fff -> 0x30100000
[   45.939690] pci-host-generic 30000000.vpci: ECAM at [mem 0x30000000-0x300fffff] for [bus 00]
[   45.948567] pci-host-generic 30000000.vpci: PCI host bridge to bus 0001:00
[   45.956098] pci_bus 0001:00: root bus resource [bus 00]
[   45.961539] pci_bus 0001:00: root bus resource [mem 0x30100000-0x30101fff]
[   45.968480] pci 0001:00:00.0: [1af4:1110] type 00 class 0xff0000
[   45.968517] pci 0001:00:00.0: reg 0x10: [mem 0x00000000-0x000000ff 64bit]
[   45.968881] PCI: bus0: Fast back to back transfers disabled
[   45.974591] pci 0001:00:00.0: BAR 0: assigned [mem 0x30100000-0x301000ff 64bit]
[   45.982475] virtio-pci 0001:00:00.0: enabling device (0000 -> 0002)
[   45.988997] uio_ivshmem 0001:00:00.0: using jailhouse mode
[   45.995644] The Jailhouse is opening.
[   46.603491] Created Jailhouse cell "AM572X-IDK-ICSS"

root@am57xx-evm:~# lspci -v

        I/O behind bridge: None
        Memory behind bridge: None
        Prefetchable memory behind bridge: None

0001:00:00.0 Unassigned class [ff00]: Red Hat, Inc Inter-VM shared memory

        Flags: bus master, fast devsel, latency 0, IRQ 179

Still, I can't generate an interrupt from the inmate to the root cell.

cat /proc/interrupts
...
179:          0     GICv2 100 Edge      uio_ivshmem
...

If I understand correctly, I need to write the value 1 to the address 0x3010000c. I'm using gic-demo to do so from the interrupt context.
Whenever the inmate writes to this address I get a dump from the kernel

[   53.306728] ------------[ cut here ]------------
[   53.311518] WARNING: CPU: 0 PID: 28 at /home/stx-ti/Projects/tisdk/build/arago-tmp-external-linaro-toolchain/work-shared/am57xx-evm/kernel-source/drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x254/0x370
[   53.330115] 44000000.ocp:L3 Standard Error: MASTER MPU TARGET PCIE2 (Read): At Address: 0x0010000C : Data Access in User mode during Functional access
[   53.343649] Modules linked in: jailhouse(O) uio_ivshmem(O) uio can_raw can ecatmc r8169 mc_gp_timer ec_master xhci_plat_hcd xhci_hcd usbcore dwc3 udc_core usb_common ti_prueth pru_rproc pruss pruss_intc snd_soc_omap_hdmi_audio omap_aes_driver omap_sham pruss_soc_bus c_can_platform c_can can_dev omap_wdt ahci_platform libahci_platform libahci libata scsi_mod ti_vpe ti_vip ti_sc ti_csc ti_vpdma dwc3_omap rtc_omap extcon_palmas rtc_palmas gpio_pisosr ov2659 omap_des gpio_tpic2810 v4l2_fwnode des_generic crypto_engine omap_crypto omap_remoteproc virtio_rpmsg_bus rpmsg_core remoteproc sch_fq_codel cryptodev(O)
[   53.397569] CPU: 0 PID: 28 Comm: irq/23-l3-app-i Tainted: G        W  O    4.14.40-rt29-gd5443cbd3b #8
[   53.397572] Hardware name: Generic DRA74X (Flattened Device Tree)
[   53.397574] Backtrace: 
[   53.397590] [<c020b220>] (dump_backtrace) from [<c020b504>] (show_stack+0x18/0x1c)
[   53.397597]  r7:00000009 r6:60000013 r5:00000000 r4:c105773c
[   53.397606] [<c020b4ec>] (show_stack) from [<c091609c>] (dump_stack+0x90/0xa4)
[   53.397615] [<c091600c>] (dump_stack) from [<c022a864>] (__warn+0xec/0x104)
[   53.397620]  r7:00000009 r6:c0bc94c8 r5:00000000 r4:d422fe40
[   53.397628] [<c022a778>] (__warn) from [<c022a8bc>] (warn_slowpath_fmt+0x40/0x48)
[   53.397634]  r9:00000011 r8:d4206850 r7:c0bc9334 r6:00000002 r5:c0bc93e8 r4:c0bc9498
[   53.397642] [<c022a880>] (warn_slowpath_fmt) from [<c051a5f0>] (l3_interrupt_handler+0x254/0x370)
[   53.397645]  r3:d42066c0 r2:c0bc9498
[   53.397647]  r4:80080001
[   53.397654] [<c051a39c>] (l3_interrupt_handler) from [<c027fc64>] (irq_forced_thread_fn+0x28/0x7c)
[   53.397659]  r10:c027fc3c r9:d4206bc0 r8:d41df100 r7:00000001 r6:00000000 r5:d41df100
[   53.397661]  r4:d4206bc0
[   53.397667] [<c027fc3c>] (irq_forced_thread_fn) from [<c027ffc0>] (irq_thread+0x130/0x208)
[   53.397671]  r7:00000001 r6:00000000 r5:ffffe000 r4:d4206be4
[   53.397678] [<c027fe90>] (irq_thread) from [<c02481e4>] (kthread+0x164/0x16c)
[   53.397683]  r10:d406bb28 r9:c027fe90 r8:d4206bc0 r7:d422e000 r6:00000000 r5:d4206c00
[   53.397685]  r4:d421e040
[   53.397693] [<c0248080>] (kthread) from [<c02079a0>] (ret_from_fork+0x14/0x34)
[   53.397698]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0248080
[   53.397700]  r4:d4206c00
[   53.397706] ---[ end trace 0000000000000004 ]---

and a different interrupt is incremented:
cat /proc/interrupts
...
23:          3     WUGEN  10 Level     l3-app-irq
...

Is there anything wrong with the cells configuration?

Is writing to 0x3010000c the right way to trigger the uio_ivshmem interrupt in the Linux side?

Can TI supply a working setup for uio-ivshmem comm between a linux root cell and a rtos inmate as a starting point?

Thanks a lot,

Nir.(Please visit the site to view this file)(Please visit the site to view this file)(Please visit the site to view this file)

Part Number:MSP430FR5989

Hi,

The MSP430FR59xx family user’s guide specifies the following :

“8.2.3.7 Wait State in Debug Mode

When the device is in debug mode, no wait state is applied. The NWAITS[3:0] has no influence in debug

mod. In debug mode (for example, during JTAG access to FRAM), the device system clock is controlled

externally and can be stopped at any time, thus FRAM access needs to be completed without wait state

cycles. The running speed of the CPU and DMA never exceeds the maximum FRAM access speed limit in

debug mode.”

Consequently when the code is executed in debug mode (with JTAG pod plugged in) what is the CPU frequency? Is it 8MHz?

What is the CPU frequency when executing the code with JTAG in free running mode?

Thank you!

Best regards,

Guillaume

Part Number:TMS320F28030

Hi,  when  running code in  the standalone  mode, The SPI bus receives two words, The first word is correct, the second word is incorrect. If the sequence is repeated,  the first word is always correct and the second is always incorrect.  Executing the exact same  code in the debug mode  this issue does not exist.

In both cases a word is sent  every second using a SPI clock of 2.5mhz.  the spi is a slave, The clock and data voltages swing 3.3 volts and look well behaved.

the SPI int is in RAM

#pragma CODE_SECTION(spiRxIsr, "ramfuncs");
#pragma CODE_SECTION(spiTxIsr, "ramfuncs");

The INT Rx code

iSpiRxData = SpiaRegs.SPIRXBUF

What am I missing?

Recently, I was working on a robot project. I need the input voltage of 30vdc-100vdc, the output power of 12V 5A and 5V 6A, which can be isolated or not, but the volume should be as small as possible.Can you recommend me some suitable solutions?

Part Number:TM4C1233H6PGE

Hello Everyone,

We have designed custom boards using TI microcontroller TM4C1233.
The microcontroller's USB module is programmed as a bulk device using one IN and one OUT pipe.
The USB part of the board's firmware is based on TI Tiva bulk example and the PC side receives data using Lmusbdll.dll on top of WinUSB driver.

In rare cases the PC application hangs and the Microsoft Message Analyzer shows USBD_STATUS_BUFFER_OVERRUN  error. After that the LmUsbdll error processing continuously calls WinUSB Abort Pipe function without any success.

The TivaWare USB Bulk class driver  defines  USBERR_DEV_RX_OVERRUN flag among USB_RX_ERROR_FLAGS but the TM4C1233 datasheet says this flag is never set for Bulk devices.

Can someone confurm if the above statement is true and possibly recommend some corrective actions besides complete application  and controller reset?

Thank you very much in advance

Best Regards

Peeter

Part Number:CC2650MODA

Tool/software: Code Composer Studio

Hy everybody!

I have a strange BLE Stack issue. My project based on simple BLE peripheral, and over a year is quite complex. I use BLE STACK 2.2.1 and TI-RTOS 2.20.1.08. I used 5.2.6 compile tool for application, XDC 3.32.0.06_core xdc tools. The app in OAD config.

The problem details:

When I build the stack with Ti v16.9.9.LTS compiler and I build the app with 5.2.6 the app is working almost properly. But when I build the stack with 5.2.6 compiler the app is running a HWI spin exec handler. I debug a little bit with ROV. I figured out, the problem is in ICall_createRemoteTasks(), beacuse when I pause the execution, in the "TASKS" field in ROV, the ICall_createRemoteTasks() with priority 5 is running.

I think is not problem with any "normal" hwi exec, like null peripheral driver call, gpio missaligment, etc.

Do anybody meet this problem? Where can I start hte debugging? Any suggestion what cause this issue?

Thanks for answer.

Best regards,

Richard

Part Number:UCC2897A

HI Sir:

   Can UCC2897 design  by flyback transformer,Any  reference design that can let us make reference?

Thanks

Gorden

Part Number:CC3120

Hello Champions ,

we are facing an issue  while trying to recover from a "Sync Loss"  happened during EMC test causing  CC3120 to get stuck .

Since during EMC test cases the software detects a "Sync Loss" event with CC3120,  we perform a CC3120 recovery restart sequence.

Some MCU's  tasks  are restarted as well right after after the "SlNetSock_select"  API timeouts .

Before to restart the MCU's task ,every binded sockets is closed  but  SlNetSock_close  fails with errno = -2005.

Once the restart procedure is completed ,  SlNetSock_create()  works .

If the restart process is repeated multiple times ,  SlNetSock_create() works a number of time equal to the available sockets descriptor.

It looks like, in case of Sync Loss event ,and because SlNetSock_close fails , Host Driver is still consuming the previous socket structure being unable to free that resources.

The issue does not happen if CC3120's recovery restart sequence is triggered when the network processor is working correctly, ( No sync Loss )

hereunder In detail the recovery restart sequence ;

* SYNC LOSS HANDLING sequence

1 - if SYNC LOSS detected, send event EV1 to SERVER TASK ( to indicate to the task to apply a recovery restart )

2 - inside SERVER task, SlNetSock_select timeouts,

3 - inside SERVER task, close(s) returns with -1 and errno = -2005

3 - wait for SERVER task to terminate

4 - sl_Stop(200 /*ms*/);

5 - sl_Start();  -- > CC3120 restarts

6 - start a new server Task.

7 - step 1 in server task ( s(n) = SlNetSock_create)  open a new socket,

                with   s(n) = s(n-1) + 1

8 - app works until the sequence is repeated enough times to saturate the available file descriptors

* SERVER TASK 

1 - s(n) = SlNetSock_create()

2 - SlNetSock_setOpt (s, .., SLNETSOCK_OPSOCK_NON_BLOCKING,..) + bind + listen

3 - SlNetSock_select

4 - accept

3a/4a if event EV1 detected, close (s), exit task

How can we make sure that the resources are properly cleaned-up in such a situation?

Thank you,

Paolo

Part Number:F28M36P63C2

The questions below are with reference to the device data sheet

SPRS825E –OCTOBER 2012–REVISED DECEMBER 2017

There seems to be conflicting information in the following two parts of the data sheet:

Chapter 4.2 column “Output buffer strength” of the table

Here it is stated that the following GPIO numbers has higher than 4 mA drive strength, most with 6 mA and a few with 8 mA:

21, 22, 23, 47, 60-62, 196, 199

Chapter 5.5 in note (2) below the table

Here it is stated that the following GPIO has a drive strength of 8 mA:

PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1, PD0_GPIO16, AIO7, AIO4.

Which information is correct?

Part Number:TPS2549-Q1

Hi,

May I know if TPS2549-Q1 is able to support USB charging up to 2.1A?

Customer of mine would like design charging controller deliver current up to 2.1A, without data transmit

If yes, what is the setting for 3 CTRL port?

and how does MCU know this function and stop communicate?

Attached is the customer's schematic for your reference 

Part Number:LAUNCHXL-CC26X2R1

Hi all,

We went through a lot of trouble lately to get the BLE stack a bit more stable and have made some progress. Not there yet unfortunately, as explained below.

Setup

• SDK 2.30.00.34 (12 Oct release)
• Simple_Peripheral example from this release
• Three bug fixes applied to the example, one change
• Three Android phones

Procedure

• Connect all phones (e.g. with NRF Connect app). Keep disconnecting and reconnecting the phones, for at least 30 minutes. For some reason, sometimes the issue occurs very fast, and sometimes it takes a long time. Often we use up to 7 phones.

Result

• Application stops advertising (no crash), and does not resume advertising ever.

Applied changes to simple_peripheral

We have applied the below bug fixes and changes to the simple_peripheral project. Without the bug fixes, the application crashes very fast if connection parameter updates are send (as any Android phone seems to do at least 3 times).

Fix 1 (we stop the clock and free it, like as is happening in the removeConn function as well):

/*********************************************************************
 * @fn      SimplePeripheral_processParamUpdate
 *
 * @brief   Process a parameters update request
 *
 * @return  None
 */
static void SimplePeripheral_processParamUpdate(uint16_t connHandle)
{
  gapUpdateLinkParamReq_t req;
  uint8_t connIndex;

  req.connectionHandle = connHandle;
  req.connLatency = DEFAULT_DESIRED_SLAVE_LATENCY;
  req.connTimeout = DEFAULT_DESIRED_CONN_TIMEOUT;
  req.intervalMin = DEFAULT_DESIRED_MIN_CONN_INTERVAL;
  req.intervalMax = DEFAULT_DESIRED_MAX_CONN_INTERVAL;

  connIndex = SimplePeripheral_getConnIndex(connHandle);
 // SIMPLEPERIPHERAL_ASSERT(connIndex < MAX_NUM_BLE_CONNS);
  if (connIndex < MAX_NUM_BLE_CONNS){


      if (connList[connIndex].pUpdateClock != NULL)
      {
        // Stop and destruct the RTOS clock if it's still alive
        if (Util_isActive(connList[connIndex].pUpdateClock))
        {
          Util_stopClock(connList[connIndex].pUpdateClock);
        }// Deconstruct the clock object
          Clock_destruct(connList[connIndex].pUpdateClock);
          // Free clock struct
          ICall_free(connList[connIndex].pUpdateClock);
          connList[connIndex].pUpdateClock = NULL;
          // Free ParamUpdateEventData
          ICall_free(connList[connIndex].pParamUpdateEventData);
      }


      // Send parameter update
      bStatus_t status = GAP_UpdateLinkParamReq(&req);

      // If there is an ongoing update, queue this for when the udpate completes
      if (status == bleAlreadyInRequestedMode)
      {
        spConnHandleEntry_t *connHandleEntry = ICall_malloc(sizeof(spConnHandleEntry_t));
        if (connHandleEntry)
        {
          connHandleEntry->connHandle = connHandle;

          List_put(&paramUpdateList, (List_Elem *)connHandleEntry);
        }
      }
  }

else
{
Display_printf(dispHandle, SP_ROW_STATUS_1, 0, ANSI_COLOR_RED"Not Matched Handle"ANSI_COLOR_RESET);
}
}

Fix 2 (change line 1296 to set connHandleEntry to NULL)

if (connHandleEntry != NULL) {ICall_free(connHandleEntry); connHandleEntry = NULL;}

Fix 3 (remove ampersand)

We removed the ampersand (see fix 1 code) as discussed in: e2e.ti.com/.../2714998

Change 1

We changed the DEFAULT_ADDRESS_MODE to ADDRMODE_PUBLIC

What's next?

After the issue occured (advertising stopped), we tried, as a workaround, to disable advertising and enable it again with a timer. We see the callback to SimplePeripheral_processAdvEvent when we issue the disable command, but when we issue the enable command, the stack doesn't send a callback to SimplePeripheral_processAdvEvent (note: we are not using 8 phones, so the devices should advertise)

static void SimplePeripheral_performPeriodicTaskAdvRestart(void)
{
 GapAdv_disable(advHandleLegacy, GAP_ADV_ENABLE_OPTIONS_USE_MAX , 0);
 GapAdv_disable(advHandleLongRange, GAP_ADV_ENABLE_OPTIONS_USE_MAX , 0);

 GapAdv_enable(advHandleLegacy, GAP_ADV_ENABLE_OPTIONS_USE_MAX , 0);
 GapAdv_enable(advHandleLongRange, GAP_ADV_ENABLE_OPTIONS_USE_MAX , 0);
}

What causes the stack to stop advertising? Is there any workaround to fix this issue? We can't  launch our product Beta, as within a few hours, people cannot connect anymore.

Part Number:DRV8842

Hello:

I purchased a CPG005_DRV88xx Evaluation Module. When install its EVM software, it shows in its "Getting Started with the EVM application" installation instruction for Windows XP and Windows 7. Is there any new version of installation software for windows 10 since my computer is new purchased and windows 10 was installed as default? Thanks.

Yiping

Part Number:LP8860-Q1

Hi team,

My customer asked me what's the best settings of DRV_HEADER[2:0] which is LED current sink headroom control.

I saw there is several setting with 3bits, so if it is set to lowest or highest, what's the difference we see? 

regards, ny