Part Number:MSP430I2040
Hi TI Team,
According to EMDC, we can generate the CCS code.
We only have MSP430i2040 Embedded Metering EVM but do not have the MSP-EXP430F5529LP (HID bridge) to the MSP-ISO (Isolation board).
Is it possible or need to have?
Regards,
Walter
Part Number:AM5718
Hello everybody ,
please two question on this latest version :
1- there is no more in in Step1 chip select : why ?
2- about SW leveling is it reccomended ? should I stay HW ?
thank you
regards
carlo
Part Number:DLP4710
I guess two of my very unusual projects would benefit from this since I wouldn't need to create secondary image planes later.
In one case I need to have a polarizing filter film on exactly half of the horizontal side of the projection and in another unrelated project I need to have a red, green and blue filters on equal sized horizontal slices of the projection. Both very unusual requirements, I agree.
My question is can I put both the polarizing filter and the color filters for both projects on the DMD itself, or is the protective glass too thick to make the filter films (0.2mm thick themselves) be exactly on the image plane and I'll need to create a secondary image plane for them in my optical system after the DMD/RTIR prism?
Part Number:TDA2EXEVM
Hi ,
I am trying to build the new PROCESSOR_SDK_VISION_03_05_00_00
And I use gmake -s -j depend and face the following error:
"System can not find the specific file."
Please help me.
Thank you.
Best Regards,
Eric Lai
Part Number:CC2640R2F
Ran out of paths to troubleshoot, so I figured I'd throw it on the forum to look for new ideas.
I have a custom board with a CC2640R2F running an application on RTOS based of the uBLE broadcaster / scanner example "uble_bcast_scan"
The application implements a state machine using several timers (via Util_constructClock), where it switches back and forth from broadcasting to scanning. I start and stop scanning and advertising using the ugap API (uble_stackInit(), ugap_scanStart(), ugap_scanSuspend(), ugap_scanResume(), ugap_bcastStart() and ugap_bcastStop()).
My application runs fine, but after 22 minutes the board stops advertising. No exceptions thrown, and everything in my app continues to run just fine. Any thoughts on what can cause the ugap stack to stop advertising after a while?
Part Number:TPS54160
Hi,
I am using the TPS54160 to generate the 5V from 50V DC input. In no load condition i am getting 5V output once i apply external load or connect to other components in the board, 5V output will drop to 1.8V.
I have checked circuit with external resistive load of 20 ohm -> 5 V output was dropping to 1.8V and output current was 75mA max.
Also tested with 150 ohm resistive load -> it was working fine (no loading effect)
Kindly support us to solve this issue
Waveform for No Load condition
PH Pin
Vin Pin
Vout Pin ->
With resisitve load of 20 ohm
PH pin
Vin Pin ->
Vout pin ->
Part Number:CC2650
Tool/software: TI-RTOS
Hello everyone,
I wondering if there any actions for supporting Zephyr OS (github.com/.../zephyr) for CC2650
Is there any actions from Texas Instruments side ?
Part Number:PROCESSOR-SDK-AM335X
Tool/software: Linux
Hi
We are using latest SDK ver5.0
1) How can I customize my rootfs before burn it to sd/mmc ?
2) Is it possible to extract the roofts gz file provided by sdk and run "opkg reomve pkg-name"?
3) Is there other tool then opkg for updating rootfs.
Thanks
Part Number:CC2630
Tool/software: TI-RTOS
In TI-MAC, the struct "macDataInd_t" and "macMcpsDataCnf_t" have member "timestamp" and "timestamp2". As document's description, the 32bit- "timestamp" is measured by "backoffs" and the 16bit-"timestamp2" is measured by “MAC timer”.What is the relationship between "backoffs" and "MAC timer"? I have researched technical manuals of IEEE802.15.4, and I know per-backoffs is 320us, per-MAC timer tick is 16us , but why the "MAC timer" 's range is less than "backoffs" 's ?
Part Number:DRV425EVM
Hi, not sure if this is the correct location to leave feedback but I see the following need and opportunity -
Can we please have the Pin Function listing provided in the DRV425EVM's datasheet (SLOU410A)? I had to make my own PDF version of this for design use, if we could have this integrated to datasheet it would be appreciated.
Thanks,
Justin
Part Number:TMS320F28377S
Hi,
Please find my configuration (code snippet), any one of trip 4,5,7 event occurs, it trigger one shot trip.
s_reg_EPWM1->TZSEL.bit.DCAEVT1 = 0x1u;
s_reg_EPWM1->TZDCSEL.bit.DCAEVT1 = 0x2u;
s_reg_EPWM1->DCTRIPSEL.bit.DCAHCOMPSEL = 0xFu;
s_reg_EPWM1->DCAHTRIPSEL.bit.TRIPINPUT4 = 0x1u;
s_reg_EPWM1->DCAHTRIPSEL.bit.TRIPINPUT5 = 0x1u;
s_reg_EPWM1->DCAHTRIPSEL.bit.TRIPINPUT7 = 0x1u;
s_reg_EPWM1->DCACTL.bit.EVT2SRCSEL = 0u;
s_reg_EPWM1->DCACTL.bit.EVT2FRCSYNCSEL = 0x1u;
s_reg_EpwmXbar->TRIP4MUX0TO15CFG.bit.Mux0 = 0x1u;
s_reg_EpwmXbar->TRIP4MUXENABLE.bit.Mux0 = 0x1u;
---
In my experiment, once trip 4 event occurred, i could see the trip zone flags were set appropriately.
s_reg_EPWM1->TZFLG.bit.DCAEVT1 as 0x1u;
s_reg_EPWM1->TZOSTFLG.bit.DCAEVT1 as 0x1u
once the trip condition is removed, unable to clear the trip flags
s_reg_EPWM1->TZCLR.bit.DCAEVT1 = 0x1u (OR)
s_reg_EPWM1->TZCLR.bit.OST = 0x1u (OR)
s_reg_EPWM1->TZOSTCLR.bit.DCAEVT1 = 0x1u
Need your help on this. EALLOW() is used before accessing this registers.
what is the diffference between for clearing OST flags using TZCLR and TZOSTCLR, which is better and when should be used.
Thanks!
Part Number:TM4C123GH6PM
Hi,
I am using timer0 to generate an interrupt every 1 second. This is working fine, but now I want to use the prescaler in order to increase the interrupt period to any number of seconds. If, with no prescaler, I am getting an interrupt every 1 second, I expect that setting the prescaler to 1 I will get an interrupt every 2 seconds and so on, but this is not working.
The code where I initialize timer0:
void timer0_init(void){
// We assume that the system clock frequency is 40MHz -> T = 25ns
/* Enable 16/32-Bit Wide General-Purpose Timer0 clock in Clock Gating Control */
SYSCTL_RCGCTIMER_R |= 0x01;
/* Ensure timerA is disabled before modifying it */
TIMER0_CTL_R &= ~0x01;
/* Select 32-Bit configuration */
TIMER0_CFG_R = 0x00000000;
/* Configure timer as periodic, count down and other functionalities as needed */
TIMER0_TAMR_R = 0x02;
/* Load start value */
TIMER0_TAILR_R = 0x26259ff; //40MHz -> to generate an interrupt every second, value to load: 40.000.000 - 1 = 39.999.999 -> 0x26259ff
// PRESCALER ??? does not have any effect
TIMER0_TAPR_R = 0xff; // tried with different values with no effect
/* Enable Timer0 interrupt in NVIC */
ROM_IntEnable(INT_TIMER0A);
/* Enable interrupt */
TIMER0_IMR_R |= 0x01;
/* Start counting */
TIMER0_CTL_R |= 0x01;
}What am I missing?
Thanks
Part Number:LMX2595
Hello:
I'm writing a three article series on modern low noise synthesizer design for publication in a major industry journal. I was planning on featuring the LMX2595 as an outstanding example of a low noise synthesizer IC with integrated VCO, along with other options such as synthesizers using the finest external VCO's.
Thus I have been closely examining its noise performance, and have noted what seems to be a consistent datasheet error in the reported normalized noise floor which represents the phase noise limit imposed by the dividers and charge pump. The flat part of the normalized floor above the 1/f corner is given as Pn1hz = -236dB, a very low number. It is the best I am aware of for any part.
Using this normalized floor Pn1hz the flat floor inside the loop bandwidth is supposed to be given by Pnflat = Pn1hz + 20log(Fvco/Fpd) + 10log(Fpd) = Pn1hz +20log(Fout) - 10log(Fpd).
But, when I compare this calculation to the noise shown in the phase noise graphs of Figs 3 to 11, I note the flat noise inside the loop bandwidth from about 20kHz to 200kHz to consistently be about 8 dB too high. It calculates as if the normalized figure of merit should be -228 instead of -236. That would still be an excellent number, just not the best on the market by a wide margin as now indicated by the datasheet.
This could be caused by the crystal reference noise floor, but this possibility is not consistent with the noise behavior shown in the phase noise graphs. It would take a crystal floor of about -151 dBc/Hz from 20kHz to 200kHz in a 100MHz reference to generate this higher in the loop BW floor, which is not typical of a higher grade reference unless its output has been padded down. However, the 1/f noise of the phase noise plots is rising at only 10dB/decade as offset frequency descends below 10kHz down to the graph limit of 100Hz. It is not being noticeably degraded by the crystal reference. That would be indicating a superb 100MHz reference, for example one showing about -135dBc/Hz at 100Hz to degrade phase noise at 100Hz by only 1dB. This is possible, but it is state of the art performance for a 100MHz quartz crystal reference, costing in the range of $400 and up. Such high quality references usually have noise floors in the range of -165 to -185 dBc/Hz over the pertinent frequency range here of 20kHz to 200kHz, not the -150 range that would give rise to the noise floors in the phase noise graphs.
I note that 1/f phase noise calculations based on the 1/f normalized figure of merit of -129 are exactly what the graphs show, so the 1/f model is very accurate.
These questions arise:
1. What crystal reference oscillator was used to take the data shown in the phase noise graphs in the LMX2595 datasheet?
2. Was the output of the crystal reference padded down so that its noise floor was worsened?
3. What normalized noise floor is proven for the part? Is the number -236 actually measured, or is it simulated, calculated, or extrapolated? Can a typical production spread in this number be provided?
4. Is there any plan to bring the outstanding normalized noise floor of the LMX2595 to a part that uses an external VCO? If there was and it is truly around -236, Texas Instruments could have the finest external VCO synthesizer product on the market to supplement what appears to be the best internal VCO product.
Thanks,
Farron Dacus
Part Number: MSP430G2553
Tool/software: Code Composer Studio
Hello,
When I execute the below code, My delay function is not executing in order to rotate my DC Motor. What's the wrong in my code.Please help me.
{ WDTCTL = WDTPW + WDTHOLD; // Stop the Watchdog // BCSCTL1 = CALBC1_8MHZ; //Set DCO to 8Mhz //DCOCTL = CALDCO_8MHZ; P2SEL &= ~BIT6; // Clear P2.6 in P2SEL (by default Xin) P2SEL2 &= ~BIT6; // Clear P2.6 in P2SEL2 while(1) { P2DIR |= BIT3 + BIT4 + BIT6; // P2.3,P2.4,P2.6 all output P2OUT &= ~BIT3 + ~BIT4 + ~BIT6; // Clear P2.3,P2.4,P2.6 // Rotate the Motor clockwise P2OUT |= BIT6; // P2.6 = 1 ,3&4_EN = 1,Motor is started P2OUT |= BIT3; // P2.3 = 1,P2.4 = 0 //__delay_cycles(100);//GIVE SOME DELAY Delay(100); // Rotate motor for sometime // Stop the motor P2OUT &= ~BIT3 + ~BIT4; // P2.3 = 0,P2.4 = 0 // __delay_cycles(100);//GIVE SOME DELAY Delay(50); // Stop the motor for sometime // Rotate the Motor Counter clockwise P2OUT &= ~BIT3; // P2.3 = 0 P2OUT |= BIT4; // P2.4 = 1 P2OUT |= BIT6; // P2.6 = 1 ,3&4_EN = 1,Motor is started //__delay_cycles(100);//GIVE SOME DELAY Delay(100); // Rotate motor for sometime P2OUT &= ~BIT6; // P2.6 = 0,3&4_EN = 0,Motor is stoped }//End of Main } void Delay(int j) { int i; for(;j<=0;j--) for(i=0;i>=0xFF;i++); }
Regards,
Darshan
Part Number:LM3481
I have the LM3481 SEPIC dev board. I had a question about using a battery as an input to a boost converter.
Could you explain why the following logic is wrong? Or if it's right, what is the solution.
In a boost converter, if you want to maintain a 12V output at 1amp or 24W, you must draw at least that much power on the input. More due to efficiency.
So the lower the input voltage goes, the more input current must be drawn to maintain that 24W on the output.
Batteries have internal resistance. So once current starts to flow, the input voltage to the boost lowers due to the voltage drop on the battery resistance, which means more input current is needed to maintain the output. Drawing more current drops more voltage on the internal resistance even more, which makes for an even higher input current. This cycle just keeps going like a "runaway" system until there is not input voltage left on the battery or something fails.
Is this scenario incorrect? I am seeing this when I put a LiPo battery as an input to the LM3481 dev board. The input current just keeps going up and up.
Part Number:LAUNCHXL-F28069M
Respected sir,
I want to do CAN repackaging. I want to copy the message id, message data high and message data low of a particular mailbox into a different variables. Then I want to give that id and data to another mailbox.
All this I am doing at receiver side. How I can do that ?
Regards,
Sunita
Part Number:MSP430FR2355
Hello,
I read throughout the datasheet sheet different values like +/-5 mV or +/-15mV, but that was more for the ADC than the DAC.
Thank you,
Louie
Part Number:LMZM23601
In the datasheet the thermal pad is said to be internally connected to GND. However in the inverting application we treat swap GND pins with Vout pins to get the negative output. With that being said the thermal pad should now be connected internally to Vout, in which case the thermal pad should not be connected to the ground plane on the PCB layout (correct?). Will there be thermal issues then if the thermal pad is left floating or is connected to the smaller Vout plane? Apologies if i missed anything in the inverting application document, but I didn't see any discussion of what to do with the thermal plane in there.
Thanks
Jason
Part Number:TUSB422
I am currently in layout for a TUSB422-based design and the via for the INT_N ball is the only laser-drilled via in the whole design. My design does not need VCONN support and the VCONN ball is currently unconnected. Is there anything that would preclude routing the INT_N line through the VCONN pad and avoiding the laser-drilled via? Leakage current into/from VCONN when VCONN_EN is disabled is not specified.