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TAS5782M: Asking for the TAS5782 bootstrap value design with 33nF

September 12, 2018, 1:30 am
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Part Number:TAS5782M

Hi Team,
For the TAS5782 bootstrap cap, could you please suggest the another cap value for customer design due to the cap component shortage?
Can customer use 33nF like TAS5729 bootstrap cap?

BR,
SHH

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Linux: Firmware crashes during EDMA access

September 12, 2018, 1:33 am
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Hi,

I want to use the EDMA. When I initialize the EDMA the firmware chrashes if it want to read or write at address 0x63300000.

Here is my Code:

 

 

Tool/software: Linux




// EDMA wakeup dependency enable
   HW_WR_REG32(SOC_CORE_CM_CORE_BASE + PM_L3MAIN1_TPTC1_WKDEP, 0x1);
   while( ((HW_RD_REG32(SOC_CORE_CM_CORE_BASE + PM_L3MAIN1_TPTC1_WKDEP) & 0x00030000U) != 0x0U) && (u32_cnt < EDMA3_MAX_WKUPDEP_CNT))
   {
      u32_cnt++;
   }

   u32_cnt = 0;
   HW_WR_REG32(SOC_CORE_CM_CORE_BASE + PM_L3MAIN1_TPTC2_WKDEP, 0x1);
   while( ((HW_RD_REG32(SOC_CORE_CM_CORE_BASE + PM_L3MAIN1_TPTC2_WKDEP) & 0x00030000U) != 0x0U) && (u32_cnt < EDMA3_MAX_WKUPDEP_CNT))
   {
      u32_cnt++;
   }

   u32_cnt = 0;
   HW_WR_REG32(SOC_CORE_CM_CORE_BASE + PM_L3MAIN1_TPCC_WKDEP, 0x1);
   while( ((HW_RD_REG32(SOC_CORE_CM_CORE_BASE + PM_L3MAIN1_TPCC_WKDEP) & 0x00030000U) != 0x0U) && (u32_cnt < EDMA3_MAX_WKUPDEP_CNT))
   {
      u32_cnt++;
   }

   /* Do EDMA init Done once in the beginning of application */
   EDMAsetRegion(EDMA3_CC_REGION);
   EDMA3Init(SOC_EDMA_TPCC_BASE_VIRT, EDMA3_EVT_QUEUE); -->Inside this function it crashes if its access 0x63300000 address

My dts-file:

&edma {
status = "okay";
};
&edma_tptc0 {
status = "okay";
};
&edma_tptc1 {
status = "okay";
};

Any suggestion?

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66AK2L06: 66AK2L06 device can support ADS8588H device ?

September 12, 2018, 1:34 am
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Part Number:66AK2L06

Dear all

     66AK2L06 device can support ADS8588H device ? Could you show me the reference design ?

     And 66AK2L06 can support DMA data sample ? (DMA is without CPU involvement, the data is stored directly from AD to memory ).

     Thanks 

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OPA2674: OPA2674 Max output power is only 19dBm that don't meet datasheet 350mA@12V

September 12, 2018, 1:36 am
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Part Number:OPA2674

Dear Sir,

This is Gordon Liu of WNC in Taiwan.

I want to use OPA2674 be a RF PA(13MHz).

Its OP1dB is only 19dBm on the below circuit  that don't meet datasheet 350mA@12V.

Could you teach me where wrong is??

12V DC_In (mA)Pin (dBm)Pout (dBm)Gain (dB)
3001212
3211312
3221412
3431512
3641612
4051712
4261812
44718.611.6
46818.910.9
48919.110.1
501019.29.2

(Please visit the site to view this file)

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E-fuse with ground isolation

September 12, 2018, 1:37 am
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Hi,

I have an application in which I need an e-fuse for protection of the Vcc rail, but in case of failure, I also need the ground to the load to be disconnected. The nominal voltage is 30 V.  I can't find any solution other than driving a FET manually for the gnd side. Is there any other solution?

Thanks,

Federico

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TMS320F28035: PWM Sync output pulse width

September 12, 2018, 1:38 am
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Part Number:TMS320F28035

Hello everyone,

I am working on a system in which I need to synchronize the PWM timebase of 2 Piccolos (TMS320F28035). In section "ePWM Electrical Data/Timing" of the datasheet, I can see that the sync out pulse width min is equal to 8 cycles, I would like to know how can I increase the sync out pulse width?

Thanks a lot for any answer!

Lam

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ADS1292: ads1292 Lead-Off detection problem

September 12, 2018, 1:38 am
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Part Number:ADS1292

Hello, we use the ads1292 chip to detect the LEAD II ECG signal. The schematic diagram of the ECG part is as follows. The ports LA, RA, RL are respectively connected to the external ECG lead wire, and the external ECG lead wire is connected to the human body through disposable ECG electrode piece. the shield signal of all external ECG leads is connected to the analog ground through port Shield, and the ports BAT+, BAT- are respectively connected to the positive and negative terminals of the external lithium battery.
When the device is properly worn on the human body, the impedance between the BAT+ or BAT-port and the human body is close to infinity. In this case,the detected Lead-Off alarm is always false and the firmware can correctly detect the ECG signal waveform. In our firmware, When any of LA, RA, RL falls off, the Lead-Off alarm is true, otherwise, the Lead-Off alarm is flase. LA, RA, RL falls off is determined by the register flag bit of ads1292.
When the impedance between the BAT+ or BAT-port and the human body is less than 1M ohm for some reason (such as sweating), in this case, the detected Lead-Off alarm is is always true , but in reality our lead is normally connected. Our question is: Does the low impedance between the BAT+ or BAT-port and the human body affect the reliable collection of ECG signals? If there is an impact, what is the minimum impedance between the BAT+ or BAT-port and the human body?If there is no impact, how can this Lead-Off alarm abnormality be solved?

Below is the ads1292 initialization code and related schematics.Thank you.

ADS_WREG(CONFIG1, 0x83);
ADS_WREG(CONFIG2, 0xC0);
ADS_WREG(LOFF, 0xF4);
ADS_WREG(CH1SET, 0x12);
ADS_WREG(CH2SET, 0x00);
ADS_WREG(RLD_SENS, 0x3C);
ADS_WREG(LOFF_SENS, 0x0C);
ADS_WREG(RESP1, 0x02);
ADS_WREG(RESP2, 0x03);

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CCS/TIDC-CC3200MODLAUNCHXL: Audio codec settings for AIC3254

September 12, 2018, 1:45 am
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Part Number:TIDC-CC3200MODLAUNCHXL

Tool/software: Code Composer Studio

Hello, TI

Please, help me!

My audiocodec is  TLV320AIC3254


I am using the default Wifi Audio App example as provided in the latest SDK.

This example samples audio in 16 bps, stereo with an sample rate of 16000.

How can i change the sample rate to: 8bps, stereo and a sample rate of 8000.

Best regards,

George

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TPS92518: Fsw calculation and result

September 12, 2018, 1:45 am
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Part Number:TPS92518

Hello

My customer chosen TPS92518 and evaluating their ES board.

Anyway, customer has question about the switching frequency

which is set by TOFF .


So, we can calculate TOFF / Fsw from TPS92518GUI and calculation tool.

( We know which is based on data sheet page 13 eq(2) & page 44 eq(37),(38) )


Customer says in case VLED is high ( VIN=55V/VLED=46.5V),

calculation result( 135KHz) and actual result (300KHz) is different.


Customer syas in case VLED is low ( 11.7V), both should be almost same.
(420~430KHz)


Where:

Duty=100% ( no dimming)

VIN= 55V
VLED= 11.7V LED  or 46.5V LED
TOFF=45 ( fixed)
ILED=1.1A ( fixed)
efficiency is 90% ( both for calculation )


Q1

Do you think this is due to efficiency becomes better when

VLED=high (duty is high) rather than duty is low?


customer is using SL310A for shottkey.

www.goodark.com
http://pdf.tixer.ru/545518.pdf


Do you think it depends on another reason?

Q2

If above was correct, do you have any advice  for n(eff) of eq (37) on data sheet p44?

Customer hope your comment for suitable equation.


for ex.

D < 50% eff =90%

D=50~ 90% then eff=94%

D>90% then eff=97%

I had attached PPT as customer's test result  capture.

Best  Regards

(Please visit the site to view this file)

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TPS65987-90EVM: Clock when Addressing 0x38 behaving strange

September 12, 2018, 1:49 am
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Part Number:TPS65987-90EVM

Hi Team,

my customer is using the EVM to programm the TPS65987D on his own board as seen below:

Programming the chip on the EVM seems to work but when trying to program the part on their own board the clock doesn't work when addressing 0x38 but works for 0x20.

As you can see the 8th clock fails when addressing 0x38. Do you know what could be the reason behind this or what we could do to fix this?

Best regards

Simon

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ADS1262: Internal resistors tolerance

September 12, 2018, 1:57 am
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Part Number:ADS1262

Dear Team,

Can you please advise on the customer question below.

We are using the ADS1262 and we would like to know what is the tolerance of the  internal 280 ohm resistance that combined the antialiasing filter.

What is the change due temperature?

Regards,

Nir

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TMS320C5517: Can I use 2 dma channels,both with interrupt?

September 12, 2018, 1:58 am
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Part Number:TMS320C5517

First, I'm using  DMA controller1 for AD/DA transmitting. I use 3 channels of DMA controller1, and all three of them use interupts, and there is no problem with that. But these three dma transmit/receive data from only one chip using I2S interface. So the timing requirment might already be met.

But when I start to use Dma control 3 with all the above 3 dma channels of DMA controller1 working, sometimes the interrupt of this Dma control 3 will not come. This Dma controller 3 is receving data from another chip using MCBSP-DMA interface.

When I stop the 3 dma channels of DMA controller1 and only keep  Dma control 3 working , the interrupt of  Dma control 3 will always come.

What's wrong with this DMA? Or I just can't use 2 dma controllers with interrupt mode?

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CCS/TMS320F28377D: CPU1 and CPU2 data interaction problems

September 12, 2018, 2:02 am
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Part Number:TMS320F28377D

Tool/software: Code Composer Studio

Because there is less interaction between CPUs, I don't want to use the IPC data exchange mode.
Use the IPC flag to judge directly, then CPU1 reads CPU2TOCPU1 space, or writes CPU1TOCPU2 space.
However, it is found in the debugging that reading and writing interactive data is correct when the program is initialized. After normal operation, the interactive data is not correct.--------When the single-step debugging is performed, write to the corresponding space (for example, CPU1 writes 0x3FC00). The data of the corresponding space has not changed?
Do I need to configure registers using the 0x3F800 and 0x3FC00 data ranges?
thank you very much!

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AWR1642BOOST: problem about installing mmWave SDK

September 12, 2018, 2:03 am
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Part Number:AWR1642BOOST

Hello,

In the quick start of AWR1642Boost, the software "TI mmWave SDK" is required to be installed. But when I click on the link, it gave me page like this(in the attachment), and I don't know how to do for the next step. Would you please give me help? Many thanks!

Best Wishes,

Kathy 

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RTOS/CC2652R: Some suggesting of ZDO and AF sending

September 12, 2018, 2:04 am
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Part Number:CC2652R

Tool/software: TI-RTOS

1, An AF sending(use AF_DataRequest and return “SUCCESS”) can generate an AF_DATA_CONFIRM_MSG message, both ZDO sending and ZCL sending can get this message. App Program can knows if AF sending valid from AF_DATA_CONFIRM_MSG. So I suggest to process AF_DATA_CONFIRM_MSG with a callback function that trigger only once after once AF_DataRequest calling. Different sending needs different processing, so the different sending should set different AF_DATA_CONFIRM_MSG callback.

2, Sometimes the ZCL endpoint needs ZDO command to search its target, it will call ZDO sending and marks sending ZDO sequence-number to judge receiving ZDO response. If many endpoint in one device in same time call ZDO sending to get its ZDO response, the endpoints must mark their own ZDO sequence-number. In my program,  a ZDO‘s AF_DATA_CONFIRM_MSG callback function can be fill into ZDO-req function's parameter struct ,and ZDO sequence-number will be returned by ZDO-req function. When ZDO‘s AF_DATA_CONFIRM_MSG callback function triggering and giving SUCCESS status, program can set a timer to wait the ZDO-response. The waiting timer remember the ZDO sequence-number and match the correct ZDO response.

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SN74AVC4T245: SN74AVC4T245

September 12, 2018, 2:07 am
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Part Number:SN74AVC4T245

 The level shifter  SN74AVC4T245 is selected between a FPGA  and CAN Transceiver 65HVD235 for the voltage translator (FPGA1.8<->3.3V CAN Transceiver). After reading the data sheet it shall be Okay for the data rate and voltage level. I just want to get a clear answer here from the TI expertise. 

Thank you for your reply!

Regards

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Linux/AM5728: EMIF configuration for DSP

September 12, 2018, 2:08 am
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Part Number:AM5728

Tool/software: Linux

Hi.

Processing of DSP's audio effect(ex. complex FFT, McASP/EDMA)  have problem(ex. audio processing time is too logner.) for memory bandwidth   when  A15 running with 2D GPU, 3DPU, IVA-HD, DSS, VPE.

now, memory bandwidth is as below it.

EMIF1 cmd_pend 87% data 51%     EMIF2 cmd_pend 86% data 50%.

 

DSP don't have any problem when A15 only running with IVA-HD, DSS, VPE.

we want to balance DDR3 bandwidth.

currently, our ddr configuration is as below it(focused on address). EMIF_1 attatched two DDR3 and EMIF_2 attached two DDR3. total memory is 2GB.

------0xFFFF_FFFFF

512MB

-----0xE000_00000

-----0xDFFF_FFFF

512MB

----0xC000_0000

----0xBFFF_FFFF

512MB ( CMEM.. )

 ---0xA000_0000

---0x9FFF_FFFF

512MB ( Kenerl code, IVA HD code/data, DSP code/data)

---0x8000_0000

I want to confirm that  0x8000_0000 ~ 0x9FFF_FFFF is in EMIF1 ?

also, I want to confirm that  0xA000_0000~ 0xBFFF_FFFF is in EMIF1 ?

we changed DSP code/data to 0xE000_00000 ~ 0xFFFF_FFFFF (am57xx-begale-x15-common.dtsi and rsc_table_vayu_dsp.h), It works very well.

but, memory bandwiddth is same to 87 %. It doesn't good.

I want that DSP2 code/data run on EMIF2, everything else(ex. A15, IVA-HD, VPE, GPU) run on EMIF1.

If it works, I think that our system don't have any problem due to memory bandwidth balance.

Is It possible ?

Thanks a lot.

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TAS5755M: TAS5755M without output issue

September 12, 2018, 2:10 am
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Part Number:TAS5755M

Hi，we use TAS5755 design as 2.1 module，however，when we write the code into TAS5755M，it cannot output voice and we find the SSTIMER pin is left floating，the code as attachment ,pls help check it and give some suggestions how to debug it,tks!(Please visit the site to view this file)

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TMS320F28379D: HRPWM: Initial synchronization for symmetric (up-down) duty control

September 12, 2018, 2:12 am
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Part Number:TMS320F28379D

Hello everyone,

I need modules ePWM1 to ePWM8 to work with symmetric high resolution duty control. All ePWM modules have the same period (TBPRD) but they have different phases (TBPHS).

I am able to obtain the desired behaviour on one ePWM by following the procedure described in the TRM (15.2.4.4.1 High-Resolution Period Configuration). However I would like a bit more information about the initial synchronization at steps 8-9.

As far as I understand:

  • The HRPWM will not work if I don't perform this initial configuration
  • The HRPWM will not work if this initial configuration is not performed while the timebase clock is running (PCLKCR0[TBCLKSYNC]= 1)

The above is very clear from the manual, but what is not very clear is what I can and cannot do after the initial synchronization. So my question is the following:

If I stop the timebase clock for some time (PCLKCR0[TBCLKSYNC]= 0) and restart it later, will the HRPWM keep performing correctly or does it need to be resynchronized?

Cheers,

Pierre

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Compiler/TMS320F28069F: Load Program Error

September 12, 2018, 2:12 am
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Part Number:TMS320F28069F

Tool/software: TI C/C++ Compiler

when I program with given examples to my custom board F28069F through Launchpad  F28027F.

It shows error in debugger window

what should be the problem?

how fix it??

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