Part Number:AM3358
Hello Champs,
SDK: ti-processor-sdk-linux-am335x-evm-04.03.00.05-Linux-x86-Install.bin
Hardware: BBB-revc + 5" LCD + HDMI
1. Modify boot: setenv optargs video=HDMI-1:800x480 HDMI can display correctly
2. Modify boot: setenv optargs video=LVDS-1:800x480 LCD can display correctly
Question： How to set uboot to display LCD and HDMI simultaneously?
Thanks.
Rgds
Shine
Part Number:AM3352
Tool/software: Linux
Dear Champs,
My customer wants to reduce booting time and is looking into NAND read speed, but can not achieve over 5.8MBytes/sec(7MB/1.2sec).
While they are looking into this, they found below abnormal clocks and every 4th clock will be longer than others - i.e. red circle is longer than blue one.
if my customer make 1st/2nd/3rd clock to be slow(long), 4th clock's duration will be shorter.
It seemed there is no way to reduce clock under 400ns for 4 clocks(100ns for each). Could you please check if this is normal?
I'l afraid their CPU clock is only 300Mhz, and this limitation was caused by this poor CPU performance.
Below is their GPMC setting.
#define M_NAND_GPMC_CONFIG1 0x00000800
#define M_NAND_GPMC_CONFIG2 0x00040400 /*0x001e1e00*/
#define M_NAND_GPMC_CONFIG3 0x00050400 /*0x001e1e00*/
#define M_NAND_GPMC_CONFIG4 0x04000600 /*0x16051807*/
#define M_NAND_GPMC_CONFIG5 0x00030707 /*0x00151e1e*/
#define M_NAND_GPMC_CONFIG6 0x04000000 /*0x16000f80*/
#define M_NAND_GPMC_CONFIG7 0x00000F48 /* cs active low */
Do you think they can reduce NAND read time more and they can achieve over 6MBytes/sec with 300Mhz CPU performance?
* SW : Processor Linux SDK v4.0
* HW :
AM3352(300Mhz)
Micron 2Gbit NAND(8bit width) - 29f2G08ABAEA
Thanks and Best Regards,
SI.
Part Number:TIDC-WL1837MOD-AUDIO-MULTIROOM-CAPE
Hi
I wonder if it is possible to share the schematic file for the WiLink 8 Wi-Fi Bluetooth Smart Audio Multiroom Cape CAD Files.
I find shematic in PDF, and also CAD files for the PCB board. But non shematic.
Redrawing from the PDF is not a complicated work, but it is a bit waste of time. It's also strange that the CAD of the PCB is there, but not the CAD of schematic,
Best regards
Mikal
Part Number:TIDC-CC2650STK-SENSORTAG
I am trying to modify simple_peripheral_cc2350stk example to handle an ADC sensor. I have created an SCS driver and incorporated it into simple_peripheral.c. The SCS generated the files into the project and it does its job as expected. I tried to add the related GATT service profile and here I failed. I created the header and source code C files using the BT studio and since I cannot add these files to the project in their proper place in the PROFILES folder I added it to the main project folder ..\Users\xxx\WorkspaceX\simple_peripheral_cc2650stk_app. I added include header statement and added the necessary code to added to the initialization code of simple_peripheral a call to BPMService_AddService() and a call to BPMService_SetParameter within the SimpleBLEPeripheral_performPeriodicTask function. Apparently the build went OK but for one cryptic problem warning "This project contains 1 unresolved buildable linked resource(s). The project may not build as expected." without being able to decipher which resource is termed "unresolved buildable linked resource". Looking at the log I could see that it "Finished building: "../BPMService.c"" and had no visible errors. However when I tried to debug it I could not put a breakpoint on the call to BPMService_AddService because the code was not available, which I think it means that it was not linked even though BPMService.obj seemed to have been linked in the build log. I looked at the "Tutorial: How to Create a Custom Bluetooth Smart Embedded Application with the CC2650DK" and it seems to recommend refactoring simple_gatt_profile to the custom profile. I stand in awe of this whole process of development!!! Simple things become monumental when trying to develop the simplest things.
Part Number:TMS320F28377D
Hello, everyone
We have a question related to interfacing Sigma-Delta Modulator AMC1303M2520 with SD Filter on F2837xD. The problem is in AMC data hold and delay time after rising edge of CLKOUT: the datasheet says, that data is held for at least 7 ns, and then changed not more than 15 ns later. The MCU latches data at rising edge of CLKOUT.
In common cases if data changes with the rising edge, then it sould be read with the falling edge and vice versa. Otherwise there is a possibility of MCU captures wrong data.
Do I have to invert CLKOUT of the AMC1303 in this case to improve reliability?
Part Number:CC1310
Tool/software: TI-RTOS
Hi all,
I am using AONBatMonBatteryVoltageGet() to get the voltage of CC1310 VCC.
AONBatMonBatteryVoltageGet(void);
This function will return the current battery monitor measurement.
The battery voltage measurements are updated every cycle.
Anyone can tell me what this cycle is? 1cycle=1tick? 1cycle=1calling?
Best Regards,
Gilbert
Part Number:IWR1642BOOST
Hey,
I have imported Driver Vital Sign Demo and uploaded code to the IWR1642 booster pack. It seems this code is not working properly. Only Range estimation is working correctly otherwise HR, RR is not working. Click to the below GIF to understand it.
Part Number:TM4C123GH6PM
I am trying to configure wide timer 0 to calculate the frequency of a pulse train (~1 kHz) using the edge timer function.
Configuration code:
//
// Set the clocking to run at 50 MHz from the PLL.
//
ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ |
SYSCTL_OSC_MAIN);
/*
* Configure the input pin (PC4) to use CCP
*/
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOC)) {}
GPIOPinConfigure(GPIO_PC4_WT0CCP0);
GPIOPadConfigSet (GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
GPIODirModeSet (GPIO_PORTC_BASE, GPIO_PORTC_BASE, GPIO_DIR_MODE_IN);
GPIOPinTypeTimer(GPIO_PORTC_BASE, GPIO_PIN_4);
/*
* Configure the timer A module of wide timer 0 in rising edge timer mode, configure timer B in periodic mode
*/
SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0);
while (!SysCtlPeripheralReady(SYSCTL_PERIPH_WTIMER0)) {}
TimerConfigure(WTIMER0_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_CAP_TIME | TIMER_CFG_B_PERIODIC);
TimerControlEvent(WTIMER0_BASE, TIMER_A, TIMER_EVENT_POS_EDGE);
/*
* Set the timer prescale and load value
*/
TimerLoadSet(WTIMER0_BASE, TIMER_BOTH, 250000);
/*
* Setup the interrupts for the timer CCP and timer timeout
*/
TimerIntRegister(WTIMER0_BASE, TIMER_A, TimerW0AInt);
TimerIntEnable(WTIMER0_BASE, TIMER_CAPA_EVENT);
IntEnable(INT_WTIMER0A);
/*
* Enable master interrupts
*/
IntMasterEnable();
/*
* Enable the timers
*/
TimerEnable(WTIMER0_BASE, TIMER_BOTH);
ISR:
/*
* Get the type of timer interrupt occurred and then clear it
*/
TimerIntClear(WTIMER0_BASE, TIMER_CAPA_EVENT);
/*
* The CCP edge capture has occurred, calculate the period of the signal if another edge
* has been captured before this
*/
uint32_t ui32_snapshot = TimerValueGet(WTIMER0_BASE, TIMER_A);
if (gui8_edge_flag) {
int32_t i32_delta;
// Calculate the time delta
i32_delta = gui32_last_timer_val - ui32_snapshot;
/*
* Check for timer overflow: since the timer is in down-count mode the new snapshot
* value will be greater than the last if overflow occurred (hence the time delta will
* be negative. If there is overflow add the timer load value to the difference to
* calculate the true time delta.
*/
if (i32_delta < 0) {
i32_delta += TIMER_PERIOD + 1;
}
/*
* Store the time delta to a buffer
*/
xSemaphoreTakeFromISR(gp_time_delta_semaphore, NULL);
circbuf_write(&g_freq_buffer, (uint32_t) i32_delta);
xSemaphoreGiveFromISR(gp_time_delta_semaphore, NULL);
} else {
// Set the flag
gui8_edge_flag = 1;
}
// Update the last value of the timer edge
gui32_last_timer_val = ui32_snapshot;
I am using a timer load value of 250000, which by my calculations should allow a minimum input frequency of 50MHz / 250000 = 200 Hz. The circbuf_write just adds a value to an array acting as a circular buffer and updates a running sum of the buffer contents (I have had this working with other code). I am using a test square wave input signal (50% DC, 500 Hz, 0-3.5 V) to cause the interrupts. I am reading the value of i32_delta using the debugger and it is fluctuating pretty dramatically: I'm not sure if this is due to the Tiva missing the edges or something else that I am missing.
Part Number:SN74HCT273
Hi All，
We found some TI SN74HCT273 needed Din hold time(th) is more than 600ns, if the Din level be switched in less than 600ns after clk rising edge, we can see switched Din status be latched.
Datasheet only defined minimum value which is 0ns. Could you please check the distribution of Din hold time? How long time we need hold the Din signal after clk rising edge to make sure it can be latched?
Part Number:IWR1443BOOST
Hi,
I was hoping that reducing the azimuth to 15 degrees or zero would give me similar results as to using a lens?
Is this correct?
I am using the IWR1443BOOST with the high accuracy lab. My intention is to measure fluid level in a water tank. Another application of mine is to just measure the closest object in a straight line in front of the sensor.
Part Number:TPS7B82-Q1
Dear TI:
The TPS7B8250-Q1 PIN 5, PIN 6, PIN 7 is NC, can these 3 pins connect to PIN 8 out ?
Thanks!
Part Number:BQ27Z561
Hi,
The BOM list in user's guide include two charger IC, BQ25890RTWR andBQ25892RTWR and actually I can see them on EVM. But there is no schematic that include these chargers in user's guide. So can you confirm it and share actual schematic of EVM?
Best Regards,
Satoshi / Japan Disty
Part Number:DS99R103
Please let me know about required AC coupling capacitor voltage.
(Are 25V or 35V no problem?)
Datasheet P20~P21 are described 100nF / 50V / X7R, but customer could not find same capacitor.
They found "100nF / 25V / X7R" or "100nF / 35V / X7R".
Best regards,
Satoshi
Part Number:CC2652R
Tool/software: TI-RTOS
Perfectly fix of the code.
1, perfect interface of processing every AF-Data-Confirm message of ZDP command's, ZCL command's and Inter-PAN command's.
2, ZNP can be freely started as ZC, ZR or ZED, and when ZC not support Touch-Link and when ZR or ZED support Touch-Link.
(Please visit the site to view this file)
Hi,
The MSP430 microcontroller inside EV2400 EVM interface board got burnt due to accidental short of +15V supply to one of the pins on the exposed port 5 connector.
The MCU P/N on EV2400 is MSP430F5529IPN. This costs only USD 7 in Digikey while it costs USD 200 to buy a new EV2400.
Is it possible that we buy MSP430F5529IPN and solder it in the board and then we flash it's firmware?
Is a bootloader required and will it be provided?
Part Number:LMR23625-Q1
Hi,
Is there any reference calculation sheet (in excel format) can be provided ??
for example, I have the inductor "COIL 22UH@100KHZ M 74437346220 SMD WURTH PB FREE" on hand, instead of "L2 Inductor, Wirewound, Powdered Iron, 2.2 µH, 4.9 A, 0.035 ohm, SMD"
and want to evaluate this (LMR23625-Q1) solution in the shortest time.
What's the parameter/component should I modify ??
Regards
Part Number:TDA2P-ACD
Tool/software: Linux
Hello,
We have a custom board with TDA2P SoC and running Linux on A15.
There is NAND flash( MX30LF1G18A) connected to TDA and want to access it from U-boot.
We have configured the NAND driver in U-boot and also added the gpmc node to the dts file and enabled the pinmux config.
When we run the code we see U-Boot log and code hangs at NAND probing.
Here is the Uboot log :
U-Boot SPL 2016.05-00010-g9551b3d-dirty (Aug 06 2018 - 12:42:11)
DRA762-GP ES1.0
board_init
********spl_boot_device******no pinctrl for hs200_1_8v
no pinctrl for ddr_1_8v
*** Warning - MMC init failed, using default environment
i2c_write: error waiting for data ACK (status=0x116)
i2c_write: error waiting for data ACK (status=0x116)
********spl_boot_device******Trying to boot from spl MMC1
reading dra7-ipu2-fw.lzop
spl_load_file_fat: error reading file dra7-ipu2-fw.lzop, err - -1
spl: error reading image dra7-ipu2-fw.lzop, err - -1
Error loading remotecore IPU2!,Continuing with boot ...
reading dra7-dsp1-fw.lzop
spl_load_file_fat: error reading file dra7-dsp1-fw.lzop, err - -1
spl: error reading image dra7-dsp1-fw.lzop, err - -1
Error loading remotecore DSP1!,Continuing with boot ...
reading dra7-dsp2-fw.lzop
spl_load_file_fat: error reading file dra7-dsp2-fw.lzop, err - -1
spl: error reading image dra7-dsp2-fw.lzop, err - -1
Error loading remotecore DSP2!,Continuing with boot ...
reading dra7-ipu1-fw.lzop
spl_load_file_fat: error reading file dra7-ipu1-fw.lzop, err - -1
spl: error reading image dra7-ipu1-fw.lzop, err - -1
Error loading remotecore IPU1!,Continuing with boot ...
spl: falcon_args_file not set in environment, falling back to default
reading single-stage-boot.dtb
spl_load_image_fat_os: error reading image single-stage-boot.dtb, err - -1
reading u-boot.img
reading u-boot.img
reading u-boot.img
reading u-boot.img
U-Boot 2016.05-00010-g9551b3d-dirty (Aug 06 2018 - 12:42:11 +0530)
CPU : DRA762-GP ES1.0
Model: TI DRA762 EVM
Board: DRA74x EVM REV
DRAM: 512 MiB
NAND:
DTS config for GPMC:
&gpmc {
/*
* For the existing IOdelay configuration via U-Boot we don't
* support NAND on dra72-evm. Keep it disabled. Enabling it
* requires a different configuration by U-Boot.
*/
status = "okay";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
compatible = "ti,am3352-gpmc";
reg = <0 0 4>; /* device IO registers */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};
Please let us know if we are missing anything.
Regards,
SwapniL B
Part Number:TIDA-00120
Hello,
We would like to use TIDA-00120 .
Our pv module has;
300W
Voc: 39.66v
Isc : 9,7 A
We would like to configure TIDA-00120 as
Max voc : 50V
Max Isc : 15A
Load is max : 15A
Battery:24V
Would you share how to modify Tida-00120 design?
Thank you
Part Number:DS90UB914A-Q1
Hi,
I understood the function of OEN/OSS_SL pin by the Table 3 and figure 9 on the datasheet.
However I can't understand how to use OEN and OSS_SL pin.
What is the benefit of the condition OEN or OSS_SL is "L"?
When should we pull down OEN/OSS_SL pin?
Best Regards,
Kuramochi