Part Number:MSP430G2553

I meet a problem with Capacitive Touch Sample code use for MSP430G2553 (msp430g2xx3_pinosc_01 get from MSP430ware). After program is compiled run on LaunchPad kit, LED1 and LED6 flash without any touch and repeat.

So is there any hardware Connections required for this ?

The sample code is as follows(Please visit the site to view this file) 

Part Number:TPS65981

Hi,

Would you kindly comment what is the minimum evaluation board setup required to test an external USB-C PD power supply?

We intend to have our design fed through TPS65981 connected to an external power supply (an off-the shelf item not monitorable), and USB data communication is not needed.

To speed the design, we'd like to test the topology using eval boards, but we are not sure if only 1 unit of TPS65981EVM is enough for monitoring the power delivery, and also not sure if DP-EXPANSION-EVM is needed.

Best wishes,

Part Number:AM3359

Tool/software: Linux

Hello,

One of my customers is using the BBB and has the following question.

"We have an embedded Linux board that's very closely based on the BeagleBone Black schematic, and we've had these devices in the field for a while. The image we currently run on them is generated by Buildroot, and uses Linux kernel 3.14.43. We're trying to add support for some new hardware over USB that requires updating our kernel to 4.10 or higher, and I've run into a bit of a wall trying to update it. I cannot get the kernel to boot after updating Buildroot to 2018.02.2 and the kernel to 4.10. I have an SD card image built using the BeagleBone defconfig in Buildroot that boots perfectly well on the BeagleBone Black, but not on our board. Historically it hasn't been a problem for us to boot BBB images considering that the hardware is so similar, so I was hoping you could help me identify what might be causing the difference, or direct me to someone who could. I can provide any additional information you might need as well."

Regards,

David

Part Number:CC2640R2F

Hi,

Is there any way to get timestamp of received packets when using ble5stack? I've read from TRM that RF core has radio timer, bAppendTimestamp flag, and timestamp field in receive buffers.

If not, what are possible ways to get the closest time stamps of incoming data or maybe the time of connection events?

Part Number:CC3220

Tool/software: TI C/C++ Compiler

Hi,

For the socket connection to the data server sl_Socket() ,sl_SetSockOpt(), sl_Connect(), sl_Send(), sl_Recv(). My understanding is that none of these are blocking except for sl_Connect(). That is, sl_Connect() may hang for a long time (tens of seconds) if there are problems with connecting to the server. I believe all other calls return immediately and generate errors in callbacks if there are issues. Please confirm that for each of the five functions listed. In particular for sl_Send() I want to be sure that this does NOT wait on any TCP handshakes but returns immediately.

1. Also, for sl_Connect(), what is the timeout for making a connection and where/how do we configure that timeout?

2. I actually just ran into a problem with sl_Recv(). When there is no data on the socket this seems to be blocking! for 5 mins if i was using 

int32_t status = sl_Recv(g_dataServerSockID, buf, BUFF_SIZE, 0);

I need a non-blocking receive function.

Just called sl_Recv() on the socket before sl_send i'll see its hang for 5 mins approx instaed of returning error so i tried NO MSG time out this

Part Number:BQ24230

I've set up a BQ23240 the same way as the data sheet suggests but PGOOD and PCHG LEDs never come on. I can power via USB DC as well as via Battery however, it's just that the LED's do not come on. Attached is my schematic set up of the charger. Any ideas what I've done wrong in setting it up? 

Part Number:IWR1443BOOST

I am trying to run High Accuracy Lab Demo (LAB4) and ran into following problem and can't proceed. 

I am using high_accuracy_14xx_lab_user_guide. When I try to do following;

Press "LOAD CONFIG FROM PC AND SEND" button and select the profile_2db.txt or profile_2de.txt* under C:\ti\mmwave_industrial_toolbox_<ver>\labs\lab0004-high-accuracy-14xx\lab0004-high-accuracy-14xx_pjt

 I get following error;

I tried both the files and get same error. How to get rid of this error?

Thanks

Kiran

The Picture got lost in the message.

The error I am getting is "Error: Missing Command cfarCfg"

If I tried to load the cfg file, I get following "Error: Missing Command dfeDataOutputMode".

Thanks

Kiran

Part Number:TMS320F28335

Tool/software: TI-RTOS

I'm currently trying to learn how to use SYS/BIOS 6.70.00.21. 

I'd like to simply blink an LED or perform some other simple I/O operation. I cannot seem to figure out how to do so and I'd appreciate some help. In reading the user guide, section E1 mentions the "GIO Drivers" but indicates that they are deprecated. I do not see any sort of replacement mentioned in that guide. Should I be using a different version of TI-RTOS? I was told in another post that the C28335 does not have TI-RTOS and that SYS/BIOS is what I ought to be using (If I'm mistaken, please let me know). Thanks

Part Number:LM2576

Dear readers,

Every now ad then I need a negative power supply with a reasonable power.  At ebay a and aliexpress the LM2576 positive output buck converters modules are sold cheap see fig1 and according schematic depicted in figure 2. Schematic 3 is an example of a buck converter with a negative power output coning from the TI LM2576 data sheets.

I examend the two schematics and looked for the differences. I noticed that basically only the negative lead of the input capacitor has a different position between the two schematics. In fig2 it is connected to the ground and in fig3 to the output. From a module perspective the changes are  that the output has changed label from output to ground,  and the ground has changed label to  negative output. Physically nothing has changed much except for then negative lead of the input capacitor.

Q1: Since this is so deadly simple I wonder if I'm making a thinking mistake. Can someone confirm if my idea to convert these modules to negative output modules is correct or not ?

Q2: If it is correct then I do have and other question. Why is the output current of the negative schematic fig3  0.7 A and not 3 Amp as it is for the positive buck power supply?. Can that be boosted somehow?

Hopefully one of you reads this and can tell me what is right or wrong here.

Regards Oscar Goos.

Fig 1: Module for sale at ebay and aliexpress

Figure 2:  Positive buck converter

Figure 3: Negative buck Converter

Part Number:LM5060

Hello,

I am planning on using a LM5060 N-Channel MOSFET High Side Driver in my design and I was wondering what is the output voltage applied to the gate following the 2.2mA discharge when the enable pin is pulled low.

i.e. is the gate pulled to Vin to prevent damage to the MOSFET by exceeding -Vgsmax ?

Thank you in advance,

Andrew

Part Number:ADS1158

we are using the ADS1158 ADC together with MAX4564 Analog switch to switch 'AinCOM'

between external floating device GND and local system measurements GND. We have observed the following pulses on the AinCom line when connected to the 

MAX4564.

See images:

The only noteworthy activity on the  chip is..   The negative 2.5V goes slightly positive for about 60ms before dropping to -2.5V.​

 However, MeasGnd  that goes to the ADC,  has quite an unusual spike at power-on, 

as well as 2 strange dips after about 6 seconds ( very consistent )

here is zoomed up image of the last two neg pulses train ..

Here is a link to a video of the screen showing the "pulses " are actually periods of ADC measurements and the GAP between the measurements.

https://goo.gl/wUcoEg​

A zoom of the first dip is here..     I'm thinking of lifting pin MeasGnd on the chip to see if the source is from u58 or the adc..  

 https://goo.gl/wUcoEg​

 We  have lifted the MAX4654 and measure the AinCOM  and there were NO pulses ... ALso, There is NOTHING strange on the MAX4654 when it is disconnected from the ADS1158 !!

What could be the problem ?  

Note:  We connected Pull down resitor on the ADC AinCom to GND and the problem disappeared ... however it happens on different test enviorement.

this is the schematics of the ADC section.

Part Number:CD74HC7046A

I suspect that the Die backside on this HCMOS device would be floating and not biased to either Vcc or Gnd.

Can you confirm ?

Thx 

Part Number:CC2564

We are using the CC2564B chipset on a Panasonic PAN1326B module connected for 3-wire communication (H5 protocol). In our design, we initially left the CC2564B CTS line floating as the datasheet seems to indicate that pin has an internal pull-up resistor (see page 13 of the datasheet). However, we found some of our devices were drawing very high current - up to 220uA when the theoretical maximum is less than 135uA. Attaching an external 10k pull-down resistor to CTS resulted in the high current devices drawing <85uA. This seems to indicate the CTS pin is actually floating on those devices an not internally pulled-up.

What are the connection requirements for the CTS pin on the CC2564B chip set and is there a pull-up resistor normally applied to the pin internally. If there is no internal pull-up, what is the meaning of the PU marking in the data sheet?

Part Number:TM4C1230C3PM

Hello,

I have the below questions from a customer:

What is  the CE and FCC compliance status for these boards?  I don’t see either mark on the product.  Can they be shipped to Europe?  Are there special rules or exceptions for dev boards?  What sort of documentation can you share?

Best,
Nadeem

Part Number:DRV135

We are seeing a similar problem in a professional audio product we are developing.
Our layout is essentially the same as Figure 29 in the data sheet, with the exception of on each output we have added a 10nF capacitor to ground and clamping diodes pointing appropriately to the supply rails that are included to act as an additional layer of transient/ESD protection.
In our prior generation of this design, the layout was essentially the same and we typically saw a stage gain of 2 within about 1% or so when the output was lightly loaded (10kohm typical) and this gain dropped very slightly, maybe by 1% or so when the loading was changed to 600ohms.
Drive levels for this testing are in the 4dBu area with the supply rails running at +/-18V, so there should be lots of headroom.
The tops of the older parts have 715EJ codes.

In the latest generation units (same schematic, updated PCB layout), the same portion of the circuit has a gain that is larger than a factor of 2 by roughly 5% or 6% at light loading, which is quite a bit larger than the gain trim tolerance specified on the datasheet.
When the load is reduced to 600ohms the gain drops more than in the previous product generation, landing somewhere below the desired factor of 2 by about 5% for a total of 10% shift from the unloaded to loaded conditions.
The latest parts are marked with 685LF codes.

So my first question is why is the nominal gain of 2 out by more than the data sheet max/min of 2%?

Also a bit confusing for me is that the Sense inputs are the feedback to the opposite phase's output driver, so the loading effect should be strongly suppressed by the magic of feedback.
Why is the feedback unable to force the drivers to maintain the appearance of a constant gain up until the device runs into its compliance margins on voltage and current?

Any thoughts or comments on this issue would be much appreciated.

Part Number:CC1310

Tool/software: TI-RTOS

Hi,

I wanted to use SPI driver in my main application to allow access on external flash. I have noticed that ram consumption increased significantly. As a result, the section between heapStart and heapEnd has been reduced and the ICall_init is always triggering an assert. Is ICALL having a specific heap section that needs to have enough room to work properly or am i missing something or doing something wrong ?

Regards,

Aurélien

Part Number:CODECOMPOSER

Tool/software: Code Composer Studio

I am installing code composer 8.0 on a linux server to be used by our development team.  I followed the eclipse installation notes about making sure everything under /opt/ti does not have group/other write permissions.  The installation works fine for the first user to run code composer.  However when a 2nd user goes to run it code composer starts with a pop-up window "Getting Started Initializer" has encountered a problem.  An internal error has occurred.  java.lang.ExceptionInitializerError.

I have diagnosed the problem starting code composer from the command line with:

bash-4.2$ /opt/ti/ccsv8/eclipse/ccstudio -clean
09:17:47 SEVERE: Failed to extract Chromium binaries into /tmp/jxbrowser-chromium-60.0.3112.113.6.15
java.lang.RuntimeException: java.io.IOException: Permission denied
at com.teamdev.jxbrowser.chromium.internal.XZExtractor.extract(SourceFile:45)
at com.teamdev.jxbrowser.chromium.internal.b.run(SourceFile:1066)
at java.security.AccessController.doPrivileged(Native Method)
at com.teamdev.jxbrowser.chromium.internal.ChromiumExtractor.extractChromiumBinariesIfNecessary(SourceFile:60)
at com.teamdev.jxbrowser.chromium.internal.ipc.IPC.<init>(SourceFile:66)
at com.teamdev.jxbrowser.chromium.internal.ipc.IPC.create(SourceFile:96)
at com.teamdev.jxbrowser.chromium.internal.ipc.IPC$a.<clinit>(SourceFile:467)
at com.teamdev.jxbrowser.chromium.internal.ipc.IPC.getDefault(SourceFile:90)
at com.teamdev.jxbrowser.chromium.BrowserCore.isInitialized(SourceFile:71)
at com.ti.chromium.browser.JxBrowser.init(JxBrowser.java:228)
at com.ti.chromium.browser.ChromiumBrowserContributor.init(ChromiumBrowserContributor.java:40)
at com.ti.browser.internal.TIBrowserPlugin.getPreferredBrowserContributor(TIBrowserPlugin.java:224)

The problem is the JxBrowser is always trying to extract into /tmp/jxbrowser-chromium-60.0.3112.113.6.15 which is owned by the first user that runs code composer it on the machine.

I can't find anywhere in the documentation about how to over ride the directory where it the jxbrowser-chromium.jar file extracts to.

Part Number:DS90UB949-Q1

Hi  all

      I have some questions about DS90UB949 and DS90UB929,please help me check them. Thanks a lot.

      1. Can the DS90UB929-Q1 support 1920*720 resolution LCD screen? If support, which deserializer can be used?

      2. When use DS90UB949-Q1 and DS90UB948-Q1 to support 1920*720 resolution LCD screen, can we connect only one cable? or must connect two cables?

     3. When use DS90UB949-Q1 and DS90UB948-Q1 to support 1920*1080 resolution LCD screen, can I take the two coaxials which used common shielding? Because the coaxials can be make more easy.

     4. Based on the 3^rd question, the coaxial can pass the 12V/1A power? Is there any reference design circuit?

     5. Please recommend reference design about FPD-LINK III,the CPU have two 24bit RGB interfaces and one HDMI interface :

       (1) support 1920*720 resolution LCD screen.

       (2) support 1920*1080 resolution LCD screen.

Part Number:AM4379

Team,

Please provide some guidance for my customer's question:

I am currently working with your AM4379 IDK evm board to test implementations of an EtherCAT master. Previously I was working with the v04.02 SDK and it seemed to have some issues with the PRU chips for Ethernet so I was forced to use the Gigabit Ethernet port to test the master we use (EtherLabs IgH master) and it was working fine. I saw that the v04.03 SDK had been released a month or so ago so I’ve been working on porting our code to that version. I did some testing to make sure everything worked and it seemed like a big improvement overall and with this version, the PRU Ethernet ports work correctly. The last thing to test was running the EtherCAT master and try to communicate with our Elmo drives and unfortunately that failed. After debugging a bit I found that we weren’t receiving any packets from the drive and so I set up a Linux machine as a switch to use Wireshark and look at the communication between the master and the slave and I noticed that the drive wasn’t sending data back. I compared the packets sent between the v04.02 SDK and the v04.03 SDK and I noticed a single difference: The packet sizes were different.

If I understand correctly, the minimum packet size has to be 64 bytes. Wireshark doesn’t display the FCS so the minimum size I expect to see in Wireshark is 60 bytes. The packets that work fine show as 60 bytes, while the packets that are failing are 64 bytes, which would mean are 68 after the FCS. Is there a known issue in the new SDK where somewhere along the Ethernet stack, one of the drivers is padding incorrectly? The actual payload on the initial EtherCAT packet is tiny (14 bytes) so it always has to be padded. I assume if the slave is trying to parse the packet and it gets the wrong size based on its payload, it’ll also read the wrong FCS and discard the packet which would explain why there is no reply. I haven’t been able to get past that initial broadcast read packets to see if the problem goes away once the payload is above 46 bytes and there’s no padding needed.

I am also looking into the master stack we are using to see if it’s doing the padding instead.

Hello every one!

I want to study about the BLDC and PMSM motor. So I need to buy the KIT for evaluation and development.

Firts, I can run the motor and check some signal which is the specification of motor as: Voltage, Current, Back EMF, Hall Sensor,...

Second, I want to build the new algorithm for speed controller ( such as Fuzzy, PID,...) and download it from Matlab to the KIT

So I don't know exactly which KIT is better for me, Can I select the DRV8312-69M-KIT or DRV8312-C2-KIT or you can suggest the other KIT 

Thank you very much.