Part Number:LMX2592

Will a life reference signal of 100MHz sinewave present cause any damage when the LMX2592 is powered down?

Part Number:BQ2040

So my project consists of using an EEPROM to program a gas gauge BQ2040 chip that is connected to a battery supply.  From this setup, I would like to read the battery specific information (time to full charge, time until discharge, etc) from the EEPROM register functions, and display it on an LCD display.  I have heard that there are certain microcontrollers that can be used in conjunction with the BQ2040 and the EEPROM to read data onto an LCD display via SMBus.  However, my issue is identifying a microcontroller that has this capability.  I also inexperienced in terms of programming the chip.  It would be helpful to receive some guidance, once a microcontroller is identified, on how to go about writing code to tell the microcontroller to read the data off of the EEPROM and display it onto the LCD.  And moreover, how to modify the code to read specific register functions (i.e. capacity remaining, battery charge percentage, etc) onto the LCD.  Does anyone have experience in this or done something similar?

Hello Friends,

 I have created a use case with the following structure:

Capture -> Dup -> Display_Video

Dup -> Null (A15)

GrpxSrc -> Display_Grpx

 I used NULL_LINK_COPY_TYPE_BITSTREAM_FILE and saved the stream in a .mpeg file.I found the size was very small for a 2 minute video from a camera having a resolution of 1280x1080(OV10640).It was only 99 KB.I was not sure how to open this file.Are there decoders to decode this file.I understand that the compression ratio is very high.Please let me know how to reconstruct the video from this file.Also please let me know if .mpeg or .h264 is the correct format to save a bitstream file.

The following is a snippet of my code

 pPrm->dumpDataType = NULL_LINK_COPY_TYPE_BITSTREAM_FILE;
	
	strncpy(pPrm->nameDataFile[0], "/mnt/usb_storage/D3.mpeg", 260U);

I have also attached the .mpeg file and .h264 file output from my code stored on SD card for reference

Best Regards,

Vijay(Please visit the site to view this file)(Please visit the site to view this file)

Part Number:WL1837MOD

We are designing an AM3354 + WL1837 product.  Due to some voltage level requirements, we'd like to use Timer 5 instead of Timer 4 when we implement Mesh Time Synchronization.  Can we use Timer 5? 

Thanks,
Matt

Part Number:TMS320C6678

Tool/software:TI-RTOS

Hello

Suppose two cores running simultanously on C6678 and accessing a shared variable  in MSMC

On core0 runs task_A

task_A
{
while ((CSL_semAcquireDirect (HW_SEM )) == 0);
..read/write shared var
CSL_semReleaseSemaphore(HW_SEM);
}

On core1 runs task_B

task_B
{
while ((CSL_semAcquireDirect (HW_SEM)) == 0);
..read/write shared var
CSL_semReleaseSemaphore(HW_SEM);
}

so far so good. Now let's add another task to core1, says task_C; also task_C accesses the shared variable

task_C
{
while ((CSL_semAcquireDirect (HW_SEM)) == 0);
..read/write shared var
CSL_semReleaseSemaphore(HW_SEM);
}

Can this cause deadlock? For example, say that Task_C has lower priority than Task_B. The following sequence cause deadlock:

1) Task_C calls CSL_semAcquireDirect and gets  HW_SEM
2) Before Task_C can call CSL_semReleaseSemaphore, Scheduler switches to Task_B (HIGH priority)
3) Task_B spins indefinitely in the while loop
4) Task_C cannot release HW_SEM (LOW priority) ----> deadlock

5) Task_A spins indefinitely 

how to avoid this situation ?

Hope my question is clear
Thank you

Part Number:TMS320F28069M

Hello,
customer uses the HV instaspin motor control kit. Is the bus voltage monitored and protected against overvoltage in case the motor generates high induction voltage?

Regards, Holger

Part Number:BQ24130

Hello,

Can you please advise on what steps we need to take to further troubleshoot this issue?

• The customer has a bq24130 EVM with no rework done.
• The input voltage is 12V
• The output is set to Single Cell (4.2V)
• There is no load connected to the output
• Multimeters are connected to the input at J1 and the output at J2
• The output voltage follows the input voltage, even if input voltage is changed.
• The status LED is blinking

Any tests the engineer can try on their bench to identify the issue are appreciated! Thank you,

Regards,
Ryan B.

Part Number:TPS568215

Since the buck regulators with D-CAP2/D-CAP3 control mode only limit the current in the low side MOSFET, I suppose these regulators do not withstand output short-circuit. Could you confirm that?

Thank you,

Antenor

Part Number:TM4C1294KCPDT

Very strange issue  PWM pulses end up on GEN1 (A) high when they were directed to (B) low.

Hardware rings out to gate driver in correct orientation (custom PCB) and firmware is configured for GPIO pins that should not be crossing these signals.

Could it be the Pin Mux decode assignments are backwards for GEN1 in (pin_map.h) and the ROM / MAP directives makes no difference. This same firmware oddly was producing correct signals on GEN1 A/B on TM4C1294NCPDT even with GEN2 A/B revered in (pins.h) defines did not effect motor runs. That GEN2 cross was corrected on KCPDT recently but it was not expected GEN1 to be reversed too as it was GEN1 on TM4C1294NCPDT and had no issues on scope captures.

Never expect GEN1 A/B reversal since a small motor was running on GEN1 few weeks ago.

Below GEN1 configuration;

    // Enable PF2 pin 44 for Phase B High GEN1 M0PWM2
    ROM_GPIOPinConfigure(GPIO_PF2_M0PWM2);
    ROM_GPIOPinTypePWM(GPIO_PORTF_AHB_BASE, GPIO_PIN_2);
    //
    // Enable PF3 pin 45 for Phase B Low  GEN1 M0PWM3
    ROM_GPIOPinConfigure(GPIO_PF3_M0PWM3);
    ROM_GPIOPinTypePWM(GPIO_PORTF_AHB_BASE, GPIO_PIN_3);


//*****************************************************************************
//
//! The GPIO port on which the phase B low side output resides.
//
//*****************************************************************************
#define PIN_PHASEB_LOW_PORT     GPIO_PORTF_AHB_BASE

//*****************************************************************************
//
//! The GPIO pin on which the phase B low side pin resides.
//
//*****************************************************************************
#define PIN_PHASEB_LOW_PIN      GPIO_PIN_3

//*****************************************************************************
//
//! The GPIO/PWM5 on which the phase B low side output resides 0x8.
//
//*****************************************************************************
#define PWM_PHASEB_LOW          PWM_OUT_3_BIT 
//*****************************************************************************
//
//! The GPIO port on which the phase B high side output resides.
//
//*****************************************************************************
#define PIN_PHASEB_HIGH_PORT    GPIO_PORTF_AHB_BASE

//*****************************************************************************
//
//! The GPIO pin on which the phase B high side pin resides.
//
//*****************************************************************************
#define PIN_PHASEB_HIGH_PIN     GPIO_PIN_2

//*****************************************************************************
//
//! The GPIO/PWM4 on which the phase B high side resides 0x8.
//
//*****************************************************************************
#define PWM_PHASEB_HIGH         PWM_OUT_2_BIT 

Part Number:OPA547

Tool/software:TINA-TI or Spice Models

Hello!  I'm trying to translate a 5V DAC voltage to a -5 to 45V signal.  The datasheet shows that this part's output can be disabled when placed in shutdown mode (either thermal or using the E/S pin).  When I simulate this, it appears that the part is actually outputting the negative rail (in my case, -12V, which is an issue) rather than floating.  Is this just an issue with simulation not knowing how to simulate a floating/tristated output or does the part actually output the negative rail when in shutdown mode?

Below is the circuit I'm using:

Let me know if any additional information is needed.  Thanks!

Part Number:BQ25606

The data sheet says 13.5V max, with a 22V absolute limit. There is a note about the peak switching ringing on the switch node. Is that what limits operating voltage to 13.5V?

What if I run this at 18Vdc max input continuously?

Is there another standalone part with power path management and at least 1A charge current that has a higher continuous operating voltage?

Part Number:TMS320F28379D

Tool/software: Code Composer Studio

Hi.

I have designed a circuit with TMS320F28379D on board, I use XDS100v2 probe. It was working ok for last two months. Today I got an error trying to upload a code :

Error connecting to the target:
(Error -2131 @ 0x0)
Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings

I have checked TDI, TMS, TCK, TDO are physically connected do device pins, nothing has changed. The default boot select pins GPIO72/84 are connected as below, so ~2.5V is at those pins:

I have performed connection test in CCS (I use XDS100v2 probe) and result is following so I assume it is ok. Running JTAG at lower TCLK didn't change anything. Any ideas? I will appreciate any prompts.

Connection test result:

[Start: Texas Instruments XDS100v2 USB Debug Probe_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\Lukasz\AppData\Local\TEXASI~1\CCS\
    ti\0\2\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Jul 21 2017'.
The library build time was '19:36:41'.
The library package version is '7.0.48.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 38 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS100v2 USB Debug Probe_0]

Part Number:TMS570LS1224

Hi, there. Since my master SPI control 2 slaves, what is the proper, good, safety way to control that? I think I cannot always write such things,

    while ((spiREG4->FLG & 0x0200) == 0);
    spiREG4->DAT1 = 0x0080 | 0x10FE0000;        // Send first 8 bit

    while ((spiREG4->FLG & 0x0200) == 0);
    spiREG4->DAT1 = (val & 0xFF) | 0x00FE0000;  // Send 2nd 8 bit

Since I do not want such dead loop. Is there have any safe way for polling method? If no, then we must use interrupt method?

Part Number:ADS54J40EVM

Is this EVM US re-export licence required?

if the parameters shown below are met or exceeded for the part  ADS54J40EVM with US ECCN 3A002.h

if US re-export license is required pls support written/email confirmation

MT applies ro 3A002.h when parameters in 3A101.a.2.b are met or exceeded 

3A101.a.2.b : Electrical input  type A-to D converter printed circuit boards or modules. having all of the following characteristics.

a.2.b.1 : Rated for operation in the temperature range frpm below -45C to above +80C

a.2.b.2 : Incorporation micro circuits identified in 3A101.a.2.a

Part Number:MSP432P401R

My goal is to achieve an I2S-compatible PCM-audio transfer using SPI and an external Codec (Maxim 9867). Main concept is:

• Short audio sample is located in memory
• Have a timer providing the frame sync signal
• Use SPI to feed the digital audio interface
• Configure DMA with timer as trigger to transfer 4 bytes:
  • 2 bytes (16 bits) left channel
  • 2 bytes for right channel (according to I2S specification)

Hence I setup TIMER_A3 with period of 543 ticks according to audio sampling frequency of 44.1 kHz. This does produce a proper frame sync signal visible in logic analyzer. The SPI on EUSCI_B1_BASE is configured properly (we will see later). So far so good...

Then I use the TIMER_A3_CCR0 as trigger for DMA_CH6 which leads to the following source code for DMA:

#define MAXIM_PLAY_DMA_CHANNEL         DMA_CH6_TIMERA3CCR0
#define MAXIM_PLAY_DMA_CH_NUMBER       DMA_CHANNEL_6
#define AUDIO_BUFFER_SIZE				0x10

#define DMA_ARBITRATION_VALUE   UDMA_ARB_2

volatile uint8_t audioBuffer[2 * AUDIO_BUFFER_SIZE];

/* Later audioBuffer will be parameter of this function */
void maximPlayDMAinit(volatile uint8_t * pData)
{
   MAP_DMA_disableChannel(MAXIM_PLAY_DMA_CH_NUMBER);
   MAP_DMA_assignChannel(MAXIM_PLAY_DMA_CHANNEL);
   MAP_DMA_disableChannelAttribute(MAXIM_PLAY_DMA_CHANNEL
                                   , UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK
                                   );
   MAP_DMA_setChannelControl(MAXIM_PLAY_DMA_CHANNEL | UDMA_PRI_SELECT
                         , UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | DMA_ARBITRATION_VALUE
                         );
   MAP_DMA_setChannelControl(MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT
                         , UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | DMA_ARBITRATION_VALUE
                         );
   MAP_DMA_setChannelTransfer(MAXIM_PLAY_DMA_CHANNEL | UDMA_PRI_SELECT
                         , UDMA_MODE_PINGPONG
                         , (void *)pData
                         , (void *)MAP_SPI_getTransmitBufferAddressForDMA(mSPIbase)
                         , AUDIO_BUFFER_SIZE
                         );
   MAP_DMA_setChannelTransfer(MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT
                         , UDMA_MODE_PINGPONG
                         , (void *)(pData + AUDIO_BUFFER_SIZE)
                         , (void *)MAP_SPI_getTransmitBufferAddressForDMA(mSPIbase)
                         , AUDIO_BUFFER_SIZE
                         );
   MAP_DMA_clearInterruptFlag(MAXIM_PLAY_DMA_CH_NUMBER);
}

void maximStartPlayDMA()
{
   MAP_DMA_clearInterruptFlag(mPlayDMAconfig.channelNumber);
   MAP_DMA_assignInterrupt(DMA_INT1, mPlayDMAconfig.channelNumber);
   MAP_DMA_enableChannel(mPlayDMAconfig.channelNumber);
   MAP_Interrupt_enableInterrupt(INT_DMA_INT1);
   MAP_DMA_enableInterrupt(DMA_INT1);
}

void dma_1_interrupt(void)
{
   uint32_t ui32Mode = MAP_DMA_getChannelMode( MAXIM_PLAY_DMA_CHANNEL | UDMA_PRI_SELECT);
   if (ui32Mode == UDMA_MODE_STOP)
   {
      /* Ping Pong Primary */
      fill_buf(audioBuffer);
      MAP_DMA_setChannelTransfer(MAXIM_PLAY_DMA_CHANNEL | UDMA_PRI_SELECT
                         , UDMA_MODE_PINGPONG
                         , (void *)pData
                         , (void *)MAP_SPI_getTransmitBufferAddressForDMA(mSPIbase)
                         , AUDIO_BUFFER_SIZE
                         );
   }
   ui32Mode = MAP_DMA_getChannelMode( MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT);
   if (ui32Mode == UDMA_MODE_STOP)
   {
      /* Ping Pong Secondary */
      fill_buf(audioBuffer + AUDIO_BUFFER_SIZE);
      MAP_DMA_setChannelTransfer(MAXIM_PLAY_DMA_CHANNEL | UDMA_ALT_SELECT
                         , UDMA_MODE_PINGPONG
                         , (void *)(pData + AUDIO_BUFFER_SIZE)
                         , (void *)MAP_SPI_getTransmitBufferAddressForDMA(mSPIbase)
                         , AUDIO_BUFFER_SIZE
                         );
   }
}

When I give it a try I can see the audio samples in logic analyzer in right order, but there are only 2 Bytes being transfered upon each trigger from frame sync signal: (please disregard the last 8 not matching bits in decoded data as a configuration issue - the signals are the same, obviously):

Of course, you might say, I simply need to change the define to UDMA_ARB_4. But this is where the real odds (and major topic of this post) are coming up: still only 16 bits are being transferred, but the 16 bits from right channel have vanished!

And this is something I neither understand nor having a clue how to resolve it.

I recently bought the TI-RSLK and I am having troubles assembling all the parts together. I viewed the curriculum and there does not appear to be instructions on how to assemble it. Can someone point me in the right direction or give me tips on how all these parts connect together?

Part Number:IWR1443BOOST

I am facing the same problem with a newly setup laptop. Is there something wrong with the link?

Hi,

Does TI have PFC Controller with clock dithering (spread spectrum) function?
Is it correct with the understanding that the following devices do not have this function?

・UCC28019A
・UCC28180

Specific product image is the following.
・R2A20104
・FA5610
Could you give me your advice?

Best Regards,
Yusuke/Japan Disty

Part Number:CC2530EM

I'm testing CC2530 sample software "PER test".

My compiler is IAR EW8051 ver 8.10.3 and tool is SmartRF05EB and CC2530EM.

I cannot set breakpoint.

What's the matter?

Part Number:AWR1243

We are also interested in developing 4 AWR1243 cascaded radar system.

We think it would be great beneficial if there is a reference design for the 4 chip cascaded radar system using AWR1243.

Can you let us know when the reference design of the 4 chip cascade radar system is public open and available?