What I want to do is to capture video from 5147 and then show it on the LCD of 8148 EVM.I am using saLoopBack for my testing. I have serveral problems needed to be clarified or fixed.

1.Video resolution captured by 5147 is not match with LCD, but interleaced video cann't do crop and scale with V4L2 IOCTL, so how can I use vpss scale function to achieve this?

2.Video ouput by 5147 is 4:2:2 YUYU format in memory. From script of setting display1 output, display1 output is set to RGB 888. Dose LCD can support YUV input or not it must be RGB? After seeting RGB888, nothing is needed in user program saLoopBack to change YUV to RGB? 

3. What are the relations between /dev/video2 and display1, VENC related capability is involved in video2? Display1 is driver for LCD? I am confused by it.

Hi,

I am doing project of CAN communication, but I am new with TMS320F28335. I want to analyze the CAN communication through PC.

I would like to ask anyone who may have experience with eCAN in TMS320F28335.

Which is the best CAN analyzer in the market? What specs that people usually looking for a good CAN analyzer?

Hi folks,

i´ve been working on capacitive RC touch sensing and looking for the lowest power for a few days with no good results. I´m using MSP430G2553 on the Launchpad and to sum up this is what i´m trying to do:

1 º Use VLO as a source for Timer_A0 to generate a 4Hz interrupt.

2º Use this 4Hz interrupt to start a scanning of the electrode using the RC method. In this case, the DCO at 16MHz is the source for the Timer_A1, so you can measure the difference in the number of cycles for the Pin-negative-edge-triggered interrupt.

3º When the pin-negative-edge-triggered interrupt is detected, the difference in cycles is measured and compared to a threshold so you can decide if there is a finger or no.

This is the code:


*********************************************************************************************************************
*********************************************************************************************************************
*********************************************************************************************************************

#include <msp430g2553.h>


unsigned int timer_count;

void main(){

    WDTCTL = WDTPW + WDTHOLD;                         // Stop watchdog timer
    BCSCTL1 = CALBC1_16MHZ;                           // Set DCO to 1, 8, 12 or 16MHz
    DCOCTL = CALDCO_16MHZ;


    BCSCTL3 |= LFXT1S_2;


    // CONFIGURO EL TIMER 0 Y EL CCR0
    TA0CCTL0 &= ~CCIE;                                 // CCR0 interrupt disable
    TA0CTL = TASSEL_2 + MC_0;                        // SMCLK and Continous up

    // CONFIGURO EL TIMER 0 Y EL CCR0
    TA1CCTL0 |= CCIE;                                 // CCR0 interrupt enable para 32768Hz es un segundo
    TA1CCR0 = 5000;                                    // The number of timer counts in the period is TACCR0+1.
    TA1CTL = TASSEL_1 + MC_1;                        // ACLK and up to CCR0

    P2SEL &= ~BIT6 + ~BIT7;                            // GPIO function
    P1DIR = 0xFF;                                    // out
    P1OUT = 0;                                        //  0

    P2DIR = 0xFF;                                    // out
    P2OUT = 0;                                        //  0

    ADC10CTL0 &= ~ENC;                                // Disable ADC conversion
    ADC10CTL0 &= ~(REFON + ADC10ON);                  // Ref and ADC10 off

    _BIS_SR(GIE);                 // Enter LPM0 w/ interrupt


    while(1){
        /* Take the active key high to charge the pad */
        TA0R = 0;
        TA0CTL = TASSEL_2 + MC_2;                        // SMCLK and Continous up
        P1OUT |= BIT4;
        _NOP();
        _NOP();
        _NOP();
        _NOP();
        _NOP();
        _NOP();
        _NOP();
        _NOP();
        // Enable interrupts (edge set to low going trigger)
        // set the active key to input (was output high), and start the
        // timed discharge of the pad.
        P1IES |= BIT4;                                    //-ve edge trigger
        P1IE |= BIT4;
        P1DIR &= ~BIT4;
        /* Take a snaphot of the timer... */
        timer_count = TA0R;
        LPM0;
        P1IE &= ~BIT4;                                    // disable active key interrupt
        P1OUT &= ~BIT4;                                   // switch active key to low to discharge the key
        P1DIR |= BIT4;                                    // switch active key to output low to save power
        LPM3;
    }

}

#pragma vector=PORT1_VECTOR
__interrupt void port_1_interrupt(void)
{
    TA0CTL = TASSEL_2 + MC_0;                        // SMCLK and Continous up
    timer_count = TA0R - timer_count;
    if((timer_count > 2500) && (P1IFG == BIT4)){
        P1OUT ^= BIT0;
    }
    P1IFG = 0;                                        // clear flag
    LPM3_EXIT;                                        // Exit LPM3 on reti

}

// Timer_A2 Interrupt Vector (TA0IV) handler
#pragma vector=TIMER1_A0_VECTOR
__interrupt void Timer1_A0(void)
{
    _BIC_SR_IRQ(LPM3_bits);                   // Clear LPM3 bits from 0(SR)

}

*********************************************************************************************************************
*********************************************************************************************************************
*********************************************************************************************************************

I achieved 67uA, but i think i´m doing something wrong, because as i see in some application notes, the current consumption in LPM3 is in the order of the hundreds of nA. This code stays in LPM3 most of the time so i think the current ought be much lower than 67uA.

Any advice?? Anything would be very appreciated! Thanks in advanced!

Alvaro G

I am using /HIB from a TM4C123GH6PM LaunchPad to control an external power switch.  VBAT to the MCU has 3.3V at all times.  The /HIB signal connects to the inputs of a 74HC1G08 (this gate is also powered from VBAT).  The output of this gate drives the switch circuit.

When the SW commands the system to go into hibernate, the /HIB pin only drops to about 2.8V.  Its only load is the two inputs of the HC1G08.  By placing a 10K to ground, the output will drop to 1.11V (this indicates that the /HIB signal appears to have a 19.6K resistance in series with the driver transistors).  There are NO components between the /HIB pin and the HC1G08 inputs.

The datasheet is mute on the subject of drive capability of the /HIB signal.  Is there any reason that the /HIB signal's drive capability should be diminished?  Do I simply have a bad part (this seems obvious, but I've replaced the chip once already and can't find a root-cause to suggest why the HIB signal is not functioning properly -- so I am reluctant to replace the MCU a 2nd time).

Cheers,

Joe

Hi,

I am debugging a DM6467 based codec engine and keep getting the message "cannot load from non-primitive location" in the watch window when I try to display some structure pointers which are cast to types other than their native type.  Can anyone tell me what the message generally means ?

Many thanks,

Mike

Hello,Everyone:

    I used AM26C32(AM26C32IDBLE/SSOP)before, We used very well. Now, I find the product status is OBSOLETE.so I want to know which product can replace the IC(SSOP)?

thank u.

#pragma or other approach.

Hi, Everyone

I need your help.
I want to use NMI interrupt with TI-RTOS on Tiva TM4C129x.

but I have a Error like this.

Only intNums > = 15 can be created.

Can you tell me how to set NMI interrupt with TI-RTOS?

Best Regaeds
Hiroyasu

While I used the AM3352 communicated to FPGA, use DMA GPMC with burst mode. But the maximum speed only 12MB. The configuration of GPMC as follows:

#define FCLKDIV   2
#define READ_ACC_CLCLE  5
#define WRITE_ACC_CLCLE  4

struct gpmc_timings gpmc4fpga_timing_burst = {
 /*config 2*/
 .cs_on = 0,
 .cs_rd_off = FCLKDIV*(READ_ACC_CLCLE+2),
 .cs_wr_off = FCLKDIV*WRITE_ACC_CLCLE,
 
 /*config 3*/
 .adv_on = 0,
 .adv_rd_off = FCLKDIV*2,
 .adv_wr_off = FCLKDIV*2,

 /*config 4*/
 .we_off = FCLKDIV*WRITE_ACC_CLCLE,
 .we_on = FCLKDIV*2,
 .oe_off = FCLKDIV*(READ_ACC_CLCLE+2),
 .oe_on = FCLKDIV*3,

 /*config 5*/
 .page_burst_access = FCLKDIV,
 .access = FCLKDIV*READ_ACC_CLCLE,
 .rd_cycle = FCLKDIV*(READ_ACC_CLCLE+2),
 .wr_cycle = FCLKDIV*WRITE_ACC_CLCLE,

 /*config 6*/
 .wr_access =  FCLKDIV*3,
 .wr_data_mux_bus = 4,
};

Hi,

I am working on TMS320f28027 microcontroller. In my project, I have a RS485 SCI bus connected to multiple microcontrollers (TMS320f28027). I need to assign a unique address to each converter to communicate with them. I am wondering if there is someway (like a unique identifier register for each microcontroller flashed by TI) that can help me address each MCU uniquely. I don't want to manually assign them unique address in code.

Thanks

Hi all,

We are using Beaglebone blacks as a starter for an AM335X-based design, I am having issues with 10MB/s Ethernet packets dropping out on Beaglebone black dev kits when sending traffic in both directions.

Is there a configuration option or kernel patch(?) I am missing?

I am using the meta-ti layer with the linux-ti-staging kernel v3.14 (more details near the end of the post).

To get the issue I am seeing to occur:

 -Set both ports on the PC and beaglebone to advertise only 10MB/s FD with ethtool:

ethtool -s eth<X> speed 10 duplex full autoneg on

 - running iperf server on the Beaglebone:

 iperf -s -u -i 1

 - running iperf client on my PC:

iperf -c 192.168.7.2 -b 64000 -i 1 -t 600 -d

The issue I am seeing is (as reported on the beaglebone via the debug serial port ttyO0)
where no packets were received on the beaglebone from 220 seconds until 247 seconds:

root@beaglebone:~# iperf -s -u -i 1
------------------------------------------------------------
Server listening on UDP port 5001
Receiving 1470 byte datagrams
UDP buffer size:  160 KByte (default)
------------------------------------------------------------
[  3] local 192.168.7.2 port 5001 connected with 192.168.7.10 port 38424
------------------------------------------------------------
Client connecting to 192.168.7.10, UDP port 5001
Sending 1470 byte datagrams
UDP buffer size:  160 KByte (default)
------------------------------------------------------------
[  5] local 192.168.7.2 port 52644 connected with 192.168.7.10 port 5001
[ ID] Interval       Transfer     Bandwidth        Jitter   Lost/Total Datagrams
[  3]  0.0- 1.0 sec  7.18 KBytes  58.8 Kbits/sec   0.009 ms    0/    5 (0%)
<<<snip>>>
[  3] 215.0-216.0 sec  7.18 KBytes  58.8 Kbits/sec   0.031 ms    0/    5 (0%)
[  5] 215.0-216.0 sec  7.18 KBytes  58.8 Kbits/sec
[  3] 216.0-217.0 sec  7.18 KBytes  58.8 Kbits/sec   0.027 ms    0/    5 (0%)
[  5] 216.0-217.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 217.0-218.0 sec  8.61 KBytes  70.6 Kbits/sec
[  3] 217.0-218.0 sec  8.61 KBytes  70.6 Kbits/sec   0.038 ms    0/    6 (0%)
[  5] 218.0-219.0 sec  7.18 KBytes  58.8 Kbits/sec
[  3] 218.0-219.0 sec  5.74 KBytes  47.0 Kbits/sec   0.075 ms    0/    4 (0%)
[  5] 219.0-220.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 220.0-221.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 221.0-222.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 222.0-223.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 223.0-224.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 224.0-225.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 225.0-226.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 226.0-227.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 227.0-228.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 228.0-229.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 229.0-230.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 230.0-231.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 231.0-232.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 232.0-233.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 233.0-234.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 234.0-235.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 235.0-236.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 236.0-237.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 237.0-238.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 238.0-239.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 239.0-240.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 240.0-241.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 241.0-242.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 242.0-243.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 243.0-244.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 244.0-245.0 sec  8.61 KBytes  70.6 Kbits/sec
[  5] 245.0-246.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 246.0-247.0 sec  8.61 KBytes  70.6 Kbits/sec
[  3] 219.0-220.0 sec  1.44 KBytes  11.8 Kbits/sec   0.079 ms    5/    6 (83%)
[  3] 220.0-221.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 221.0-222.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 222.0-223.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 223.0-224.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 224.0-225.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 225.0-226.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 226.0-227.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 227.0-228.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 228.0-229.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 229.0-230.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 230.0-231.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 231.0-232.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 232.0-233.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 233.0-234.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 234.0-235.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 235.0-236.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 236.0-237.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 237.0-238.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 238.0-239.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 239.0-240.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 240.0-241.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 241.0-242.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 242.0-243.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 243.0-244.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 244.0-245.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 245.0-246.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  3] 246.0-247.0 sec  0.00 Bytes  0.00 bits/sec   0.079 ms    0/    0 (nan%)
[  5] 247.0-248.0 sec  7.18 KBytes  58.8 Kbits/sec
[  3] 247.0-248.0 sec  1.44 KBytes  11.8 Kbits/sec   0.150 ms  151/  152 (99%)
[  5] 248.0-249.0 sec  8.61 KBytes  70.6 Kbits/sec
[  3] 248.0-249.0 sec  1.44 KBytes  11.8 Kbits/sec   0.144 ms    4/    5 (80%)
[  5] 249.0-250.0 sec  7.18 KBytes  58.8 Kbits/sec
[  3] 249.0-250.0 sec  5.74 KBytes  47.0 Kbits/sec   0.121 ms    3/    7 (43%)
[  3] 250.0-251.0 sec  4.31 KBytes  35.3 Kbits/sec   0.102 ms    2/    5 (40%)
[  5] 250.0-251.0 sec  7.18 KBytes  58.8 Kbits/sec
[  3] 251.0-252.0 sec  8.61 KBytes  70.6 Kbits/sec   0.074 ms    0/    6 (0%)
[  5] 251.0-252.0 sec  8.61 KBytes  70.6 Kbits/sec
[  3] 252.0-253.0 sec  7.18 KBytes  58.8 Kbits/sec   0.064 ms    0/    5 (0%)
[  5] 252.0-253.0 sec  7.18 KBytes  58.8 Kbits/sec
[  5] 253.0-254.0 sec  8.61 KBytes  70.6 Kbits/sec
[  3] 253.0-254.0 sec  8.61 KBytes  70.6 Kbits/sec   0.053 ms    0/    6 (0%)
<<<snip>>>
[  5]  0.0-600.3 sec  4.58 MBytes  64.0 Kbits/sec
[  5] Sent 3267 datagrams
[  5] Server Report:
[  5]  0.0-600.3 sec  4.58 MBytes  64.0 Kbits/sec   0.051 ms    0/ 3267 (0%)
[  3]  0.0-600.3 sec  4.35 MBytes  60.7 Kbits/sec   0.061 ms  166/ 3267 (5.1%)

Full logs from both my PC and the Beaglebone, and Wireshark in attached files.

There are no packets missed by my PC, but I have to run the test is bi-directional mode ('-d' option) to see the issue.

I have tried different data rates both faster and slower but the issue persists, the issue also occurs with TCP based tests (omitting the '-u' option from both command lines) where the test simply blocks until the connection is restored.

There are no errors (or any messages at all) reported via dmesg for the duration of the test.

I am building the OS via Yocto and have reduced the setup to a basic system with

 - poky,                                 git rev: "daisy:a4d8015687cf9ddd6ef563e29cf840698f81c099"
 - meta-openembedded, git rev: "daisy:662cf409c1175450699d498085f3c894e0fe81d0"
 - meta-ti,                            git rev: "daisy:df04699e3aae0ccfa88369117d6d20a9b46a6b26"

I have attached the only files I have modified for my setup:
 - /opt/r2/ethernet-issue/poky/build/conf/bblayers.conf
 - /opt/r2/ethernet-issue/poky/build/conf/local.conf
 - /opt/r2/ethernet-issue/poky/meta/recipes-core/images/core-image-minimal.bb.

Hi.

i just received sevral new CC3200 sample chips of which the chip verison is 1.33, and i replaced old v1.21 chip with v1.33 chip on the CC3200 moduel.

i use CC3200SDK_1.0.0 , CC31xx_CC32xx_ServicePack_1.0.0.1 and GCC compiler. everything works fine if i don't add any function related to simple link. if i add simple link function,  when calling  sl_Start(), CC3200 force itself to keep resetting.

Any help would be appreciated.

Best Regards,

Eugene.

Dear Sir,

I have a question how many clock cycles are required to get performance specified in datasheet after clock started running.

I found Overall latency = ADC latency +tPDI in the ADS42LB69 datasheet (p7). Default latency after rest is sepcified typ 14 clock cycles,  and Clock propagation delay is specified typ 10.5ns and max 13ns.

Is above formula a right wait time until datasheet guranteed performnace will be available after clock started running?    

It does not have maximum value of the Default latency after rest, so how many maximum clock cycles the system should wait for the performance in safe?

 Best regards,

Masa Katayama   

Hi,

I have a question about AM335x warm reset.

At our customer, their customer board is having strange behavior
at external warmreset(nRESETIN_OUT) and GPIO.
nRESETIN_OUT are connected to reset switch.
If this reset switch is pushed, GPIO of C15/C16 (ZCZ package) will carry out
the same behavior as nRESETIN_OUT.

Is there any information for this behavior?

And sometimes when they push this reset switch, MPU will freeze until POR.
They are figuring out what will cause this freeze problem.

best regards,
g.f.

We use the AM3352 chip to communication with FPGA by GPMC at burst mode. The GPMC bus width is 16bit, I have a question which is that the GPMC can support 16 words length burst?

Hi...

I am using LMP90100 in my application.

Registers reading after configuration are not showing the actual data whats written.

And also GPIO pins as outputs pulled to high also not giving high at output.

So please help me how to check the healthiness of LMP90100.

Thank you in advance..

Hello,

My customer uses the SN74AVC24T245.

He uses the device to translate a signal from CPU(1.8V) to SoC(3.3V).

It is occurred a strange function at one of a channel that drive a LED.

I attach the file of timing chart and block diagram.

(Please visit the site to view this file)

After the CPU initialize time, right operation B-port is Low, but B-port
is High level actually.

The A-port voltage is less than 150mV, there is no noize.

But when he uses a pull-down at A-port by 10kohrm, it is a normal operation.

A strange function occur using another channel or another sample.

Could you tell me the cause of the strange function?

Is it too long CPU initialize time?

Regards,

Naoki Aoyama

Hello, all

Now we have one inquiry regarding starting up output on TXB0304 from our customer.

Please refer to the item below, and feedback us with your comment.

We found one pulse on B-Port when starting up this device.

The detailed configuration of this device is as below;

A-PortA: 1.8V
B-PortB: 3.3V (This port is starting up 3ms earlier than A-Port)

During this 3ms, we found 1ms pulse on B-Port, if this port is Hi-Z or Pulldown. 

As solution of this issue, we tried to have B-Port to Pulldown or OE signal to HIGH after 1.8V was established. However, there still found the pulse.

For your reference, please see the device configuration below;

(Please visit the site to view this file)

Please let us clarify how we could resolve this issue.

We thank you in advance for your information.

Best regards,

I have converted a Solar DC DC inverter control suite project, from F28035 to F28027.

Code is running properly, Cpu Timers are working. 

Interrupts are also getting generated in the code by:

IER |= M_INT3; // Enable CPU INT3 for capture interrupt
PieCtrlRegs.PIEIER3.bit.INTx4 = 1;

But, the corresponding ISRs are not getting called.