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RM48L930: SCI/LIN baudrate fine-tuning using 4-bit fractional divider M

March 29, 2018, 8:48 am
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Part Number:RM48L930

Support Path: /Product/Help with Device Selection/

Hello,

The Hercules reference manual (spnu503b.pdf) section 25.2.3 (SCI Baud Rate) states:

The SCI/LIN has an internally generated serial clock determined by the peripheral VCLK and the
prescalers P and M in this register. The SCI uses the 24-bit integer prescaler P value of BRSR register to
select the required baud rates. The additional 4-bit fractional divider M refines the baudrate selection.
In asynchronous timing mode, the SCI generates a baud clock according to the following formula:

SCICLK Freq = VCLK / ( P + 1 + M/16 )

and   Async baud rate =  SCICLK Freq / 16

My application calls for a baudrate of 115700 baud (not 115200), when running at VCLK = 40 MHz.  A value of P = 20 and M = 10 would result in a baudrate of 115607, which is close enough.

My question:  HALCoGen does not expose the M setting when configuring SCI or SCI2.  The ref manual states that M is set via the BRSR register bits 27:24.  But in SCI mode, the HALCoGen SCI.c driver code does not use the BSRS register, it uses the BAUD register.

Is the reference manual incorrect?  In SCI mode, can I fine-tune the SCI baudrate using the 4-bit M field in register BRSR?   How to do it?

thanks,

Keith

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CCS/MSP430G2553: Sample code for MSP430F2553

March 29, 2018, 8:52 am
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Part Number:MSP430G2553

Tool/software: Code Composer Studio

Hello,

I am looking for sample code similar to C 2000 in control suite for MSP430G2553. Can anyone share link with me for the MSP code for MSP430G2553?

Thank you!

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Patching Wilink 8.7 SP3 onto Sitara SDK 4 to fix WPA2 Issue

March 29, 2018, 8:55 am
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Part Number:WILINK8-WIFI-NLCP

Tool/software: Linux

Following the WL18 integration guide: WL18xx_Platform_Integration_Guide , The are build scripts for generating kernel modules, firmware, hostapd, and other tools.

The WPA2 issues post in this forum states that using wilink 8.7 SP3 will patch the vulnerabilities.

There are support posts on SDKv4 which state that the kernel modules (or 'modules' step in the build script) is not required in sdkv4 and Appendix A states that there is a single patch that updates three files in the SDKv4 kernel sources.

So to get Sitara SDKv4 patched with the latest Wilink 8.7SP3 package and no longer vulnerable to WPA2 key reinstallation attacks, is it enough to install firmware,utilities, and other software(leaving out the modules step) using the following commands using the build scripts and leave the .ko files generated by running the TI SDKv4 kernel build after applying the patch from Appendix A?:

  1. build_wl18xx.sh init R8.7_SP3
  2. build_wl18xx.sh libnl
  3. build_wl18xx.sh hostapd
  4. build_wl18xx.sh wpa_supplicant
  5. build_wl18xx.sh firmware
  6. build_wl18xx.sh utils
  7. build_wl18xx.sh scripts

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DAC38RF84: JESD204B Subclass0

March 29, 2018, 9:04 am
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Part Number:DAC38RF84

Hi,

We only use one DAC and one FPGA for our application with  a speed lane about 4.6Gbps ( *4)

We are looking at he possibility to DAC38RF84 in sub0.

The datasheet say that "some functionality has been implemented to support Subclass0 operation"

Can you please provide more details about the functionalities which are not availables in this subclass?

What is the higher speed that we can use in this mode if limitations implies please?

Best Regards

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LMX2595EVM: follow up to earlier bricked board post

March 29, 2018, 9:07 am
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Part Number:LMX2595EVM

Dean,

I appreciate the response.  I still have some troubles.

I can communicate with the 2492 device with either of my USB2ANY boards.  

For step 2, your comment was instructive, I didn't realize the VCO on the EVM board was tuned for that region.  But I don't see any ramping, even in the 9.4 - 10.8 GHz region.  All I see is a CW peak on my Spectrum Analyzer.  I can move it from 9.4 to 10.08 GHz.  

Furthermore, when I try and "Read All Registers", the GUI works fine until I get to register 0x18 and then the GUI quits.  This has happened many times.  There are no python errors like the divide by 0 issue with my 2595 board.

For Step 4, I tried to load the default, and nothing changed.  I also deleted the .tcb file and I still cannot power up/power down.  When I load in a saved .tcs file, that I *know* worked two days ago, I still have the divide by 0 problems, with no responsiveness from the board.

I appreciate your help, it is nice to know I have an expert to call on for help.  On a positive note, you directed me to where the python code is for the GUI, so now when I get this working I have example code to go port into my micro.  Much appreciated!

Cheers, Darren

P.S.  In order to post the screen grab, the forum made me create a new post and I could not figure out how to make the post as a reply on my other thread.  For reference, this thread refers to this post. 

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CC2564: multiple SPP LE connections

March 29, 2018, 9:07 am
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Part Number:CC2564

Hello,, we are using SPP+LE profile. We want to connect up to 4 external devices through low energy to the CC2564, how to configure the stack?

At the moment we can connect only 1 external device (iPhone) to our CC2564 board (we can send/receive data through low energy)

Please let us know.

Thanks/Florent

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LAUNCHXL-CC2650: simple_eddystone example does not run on launchpad CC2650

March 29, 2018, 9:08 am
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Part Number:LAUNCHXL-CC2650

Hello,

though I have read some threads dealing with similar problems here, the simple_eddystone example doesn t work on my launchpad cc2650.

I got the CCS project from github like described in the application notes ( github.com/ti-simplelink/ble_examples/tree/ble_examples-2.02.09.13 )

First I tried the branch later the tag like mentioned in brackets.

I use CCS 6.2.0  and I have downloaded compiler version 5.2.6  afterwards.

I ve installed ble_sdk_2_02_01_18  together with TI-RTOS 2.20.01.08.

Afterwards I copied the following files from the github zip file to the ble_sdk folder

Eddystone Beacon:
ble_examples/examples/cc2650lp/simple_eddystone
ble_examples/src/examples/simple_eddystone/cc26xx
ble_examples/src/profiles/EddystoneURLCfg

Build works (no errors and no warnings).

But while debugging the application I noticed that it s caught in an infinite loop at 0x1001bbd8 or something like that.

I tried to increase the stack size like mentioned in e2e (but there were various definitions along the project - not sure that I ve modified the correct ones)

result: get caught at another position ... but still no beacon detectable by eddystone validator neither beacon scanner app

Connection to target verified and ok. SmartRF Flash Programmer works too. Hardware seems to be correct set up ... but the example does not switch leds on, doesn´t it ?

What could be wrong. Does the example run on your device. If true can you send your project as a zip file to me ?

Best regards,

stefan

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TDC1000: How to connect the TDC1000 with transfomer

March 29, 2018, 9:11 am
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Part Number:TDC1000

Hi Team,

I would like to know how to connect the TDC1000 with transformer. In order to boost 5V, should we use TDC1000+SN6501+transformer?

Thanks!

Best,

Nancy

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DM505: Support for DM505

March 29, 2018, 9:15 am
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Part Number:DM505

Support Path: /Product/Help with Device Selection/Processor solutions/Digital signal processing devices/

Am want to use DM505L in my design, Please clear the below.

1) In DM505L can i develop by using only DSP with CCS without any RTOS support for ARM. i.e can i develop independently without arm coding to reduce the code complexities if required.

2) If required can i disable ARM Cortex and use only DSP blocks to make the power saving .

3) Can you provide Booting process for DSP .Is it mandatory that first ARM should Boot then DSP.

4) As Development kit available for DM505x.does the kit available separately for DM505L (Single core) to reduce the cost less than DM505M(Dual core).

Please clear the below as soon as you can there by i can able to select the processor for my design.

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CDC3RL02: The specification of Master clock input (MCLK_IN)

March 29, 2018, 9:20 am
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Part Number:CDC3RL02

Hi,

I designed my clock circuit using CDC3RL02, I have a question about MCLK_IN of this buffer.

Does the buffer accept an AC-coupled clock signal as input for MCLK_IN? (The input signal into MCLK_IN in my design is as AC-coupled sinusoid signal from OCXO) 

It is specified the specification of MCLK_IN on page 6 the datasheet as below. I think this means that input signal into MCLK_IN should be DC-biased signal. 

But, on page 11 of the datasheet, there is an AC-coupling capacitor inside the MCLK_IN input as below. I think this means that an AC-coupled signal is also acceptable. So, I am confused. Is it possible to be applied AC-coupled sinusoidal clock into MCLK_IN?

I would appreciate your advice.

Thanks.

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HD3SS3412A: Maximum Operating Temperature

March 29, 2018, 9:23 am
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Part Number:HD3SS3412A

Hello,

I was looking at the HD3SS3412A datasheet and comparing it with ti.com.   I noticed that page 6 of the datasheet indicates a maximum operating temperature of 70oC:

But ti.com indicates a -40oC to +85oC temperature range:

Which one is correct?

Don

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SENSORTAG-SW: rfWsnNodeExtFlashOadClient LCD support

March 29, 2018, 9:23 am
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Part Number:SENSORTAG-SW

Hi.

Is there LCD support for the firmware rfWsnNodeExtFlashOadClient_CC1350STK_tirtos_ccs for cc1350-sensortag?

I tried setting the symbol BOARD_DISPLAY_EXCLUDE_UART in ARM predefined symbol, compiled in CCS7.4, flashed to target connected to debugger devpack using Flash Programmer 2.
Then i removed the debugger, put the LCD, inserted battery and LED started blinking periodically but nothing appear on LCD.

Can you please help? Can the LCD work with this example?
I am looking for 15.4 example (not dualmode, not BLE) with LCD driver for CC1350-SENSORTAG. Is this kind of thing exist?

Thank you very much

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CSD88599Q5DC: Can this replace FETs in PMP21278

March 29, 2018, 9:34 am
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Part Number:CSD88599Q5DC

Hi team,

My customer is thinking of implementing this reference design in their system, but the FETs are pretty pricey.

Can the above FET module replace the four FETs on the input stage of that ref design? And do you have a good,cheap FET module recommendation to replace the lower voltage output stage?

Thanks,

Brian 

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ADC128S102: Differences in 5962-07227 and ADC128S102 input impedance

March 29, 2018, 9:35 am
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Part Number:ADC128S102

I need to understand the difference in the 5962-07227 and ADC128S102 input impedance.

We are currently using both parts in a similar application. We have noticed a difference between them.

Thanks,


Carolyn Sleeper

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CC2541: How to use internal flash memory (basic read-write-erase operations)?

March 29, 2018, 9:36 am
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Part Number:CC2541

Hi,

I need some help with HalFlashRead / Write / Erase functions.

I'm trying to write and readback some small amount of data.

After read I get only 0xFF, I suppose, I'm reading from wrong address.

Here is part of code:

uint8 send_buf[10] = {0x01, 0x02, 0x03, 0x04, 0x05,0x06, 0x07, 0x08, 0x09, 0x10};
uint8 get_buf[10] = {0}; // inits as zeros

void main(void)
{
   //------------------- HAL PROTOTYPES
   //void HalFlashErase(uint8 pg);
   //HalFlashWrite(uint16 addr, uint8 *buf, uint16 cnt);
   //HalFlashRead(uint8 pg, uint16 offset, uint8 *buf, uint16 cnt);
   
   //lets say I need to write to page #4 (which is located at address 0x2000)
   
   uint8 pageNum = 4;
   uint16 pageAddr = 0x2000;
   HalFlashErase(pageNum);
   HalFlashWrite(pageAddr, send_buf, 10);
   
   //readback
   uint16 offset = 0; // as I understand, this should be non-zero when I'm trying read something at middle of page
   HalFlashRead(pageNum, offset, get_buf, 10);

  // and get_buf is filled with 0xFF
}

Please advice about what am I missing. 

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CCS/TMS320C6455: I am converting a project from CCS v3.3 to v7.4 and am having trouble with a generated .s62 file.

March 29, 2018, 9:53 am
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Part Number:TMS320C6455

Tool/software: Code Composer Studio

I am converting this project and when I build a .s62 file is generated that produces build errors. I was using SYS/BIOS v6.42 previously in the project, but because of other problems reverted to DSP/BIOS v5.42. I am using windows 7, and CCS v7.4 .

Thank you

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TPS563219A: Design question_ESR_internal regulator voltage

March 29, 2018, 10:03 am
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Part Number:TPS563219A

Please help to provide the calculation form of TPS563210A and TPS563219A.

Furthermore, please answer the following of questions.

 

 

  1. How does determine the minimum ESR of ceramic output capacitors?  

 

  1. Please provide the internal regulator voltage of TPS563210A and TPS563219A.
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AM4376: AM4376 RGMII interface

March 29, 2018, 10:08 am
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Part Number:AM4376

We are interfacing to a BCM switch with a 2.5V RGMII interface.

IS there a way to avoid using level translators? Possible to power up the RGMII (1) interface from 2.5V's  ( VDDIO11)

If usage of 2.5V is not possible, which translators would you recommend?

thanks

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LMZ31520: Decreased power output observed

March 29, 2018, 10:10 am
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Part Number:LMZ31520

Hi,

I have designed a board with LMZ31520RLGT.

The schematics part is as below 

Please let me know if anything I have missed out here.

We are observing a 1.92V on the output, we have checked the resistor before mounting and its 324E exact.

(The design was done with a buffer of 2A from the actual requirement.)

What could be the possible reasons for low output voltage?

Thanks & Regards,

Nanjunda M

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DAC8750: DAC8750 TVS Selection

March 29, 2018, 10:14 am
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