Part Number:TCA6424A

any plans by TI to EOL this part in the next 5 years ?

Part Number:MSP430FR5969

Hi,

     I am trying to use the same timer for sourcing the ADC and then running UART int he timer interrupt.But it is not working.If I use two timer interrupts then also no results .

Is it possible to use it in this way.I am not sure about how to go about  it.I am suppose to sample the ADC for 100ms in 1 second and print the data on uart every 10 seconds.

It would be really great if somebody could help me in clearing this concept or give a suggestion for implementation.

Thanks 

Regards

Stuti Jain

Part Number:UCD9081

Any plans by TI to EOL this part in the next 5 years?

Part Number:LM53635-Q1

Hi,

My customer requires a detail of the spread spectrum and we are referring "8.5 Spread-Spectrum Operation".

Q1.

About "Spread-spectrum pattern frequency", is "Random Pattern" repeated as below if it is 8Hz?

Q2.

If above picture is yes, how many steps does it have per a random pattern?

In other words, how many times does switching frequency vary during a random pattern?

Q3.

Could you provide the material mentioned a mechanism of LM536x5 spread spectrum?

My email address is 'kuramochi@fujiele.co.jp'.

Best Regards,

Kuramochi 

Part Number:CC2530

Tool/software: WEBENCH® Design Tools

How to reset zigbee router if voltage down below perticular value,

For example if I want to reboot zigbee router if VDD decrease below 2 volts????

How can I implement this........????

Hello,

reading through the Technical Reference Manual for TDA2XX I understood that the PCIe controller instantiates 2 subsystems which can operate in following usecases:

1) Only subsystem 1 working in x1 mode

2) Only subsystem 2 working in x1 mode

3) Subsystem 1 and subsystem 2 both working in x1 mode simultaneously

4) Subsystem 1 working in x2 mode while subsystem 2 cannot be used

I'm working on PROCESSOR_SDK_VISION_03_02_00_00 and have successfully tried usecases 1 and 4. However I'm trying variant 2 and 3 right now. When I do the programming of the PCIe subsystems I refer to the tables that contain typical programming sequences that I found in Technical Reference Manual for TDA2XX. The testing is done using PCIe example from PDK.

I'm working on utilizing only subsystem 2 in x1 mode, first. The initialization of the clocks and PHY pass correctly but when it comes to choosing which type of pcie the subsystem will be (RC or EP) the execution hangs. Important thing to say is that this happened for the first time when programming SS2, haven't had those problems with SS1.

Therefore I have a few questions:

1) The SoC that I'm using is TDA2SX whereas the documentation that I refer to is for TDA2XX. Are those two the same and can I assume that there are indeed two PCIe subsystems in my SoC?

2) If there are 2 PCIe subsystems, why does the execution hang during RC/EP mode choice? I was mimicking the code that is present in the test for SS1 but also following the programming sequence table from TRM (that is for pcie_app.c). In the RC and EP parts of the test I just replaced every ocurrence of "SS1" with "SS2" (the code of course compiles and builds and I am able to run it).

Thank you in advance.

Regards,

Nick

Part Number:TIDA-00078

The CDCE62005 chip on the EVM has an external reference input at J8. I would like to use a external clock with test equipment (10MHz) to sync up all the signal to the same reference.

The CDCE62005 GUI does not seem to be operational, when I click on it from the main GUI, there is no additional GUI for CDCE62005 that pops up. 

Any recommendation for enabling external reference to the CDCE62005?

regards,

Juswanto

Part Number:WL1807MOD

Customer is migrating from WL1801 to WL1807 to add 5 GHz support.  They are using a single antenna configuration.  Please advise on configure-device.sh SISO40 prompt.  Should it be y or n?

Are you using a TI module? [y/n] : y
What is the chip flavor? [1801/1805/1807/1831/1835/1837 or 0 for unknown] : 1807
Should Japanese standards be applied? [y/n] : y
How many 2.4GHz antennas are fitted? [1/2] : 1
How many 5GHz antennas are fitted (using 2 antennas requires a proper switch)? [0/1/2] : 1
Should SISO40 support be applied? [y/n] : ?

Thanks,
Mark 

Part Number:BQ25703A

I'm working on a handheld device with internal battery pack and charger IC. You only have to connect a USB to charge the battery pack. In my design I'm using the BQ25703A and I'm playing around with the EVM. I came across a problem for my design.

I have 4 series NiMH batteries and thus have the CELL_BATPRESZ set for 4 batteries. When starting in this setting the starting charging and system voltage are way to high! Only after setting the registers it will become correct. My first solutions was to pull the CELL_BATPRESZ to zero, set the registers and pull him up again, but the registers would still go to the high settings. I also tought about setting CELL_BATPRESZ for 1 or 2 series batteries and the starting outputs are low enough, but I can't start charging because of an over protection security that will keep setting after I reset it by pulling the register.

The only solution left in my mind is protect the circuit by hardware. (sorry for the drawing skills) I thought of something like the attached drawing. And I was wondering if this is really the only solution and/or there is still another option I hadn't thought of yet. And if in this design the OTG would still work.

I'm thinking of the worst case scenario. The battery is completely empty and thus the charger would start with high voltage when given power. I will power the circuit with the USB power and the powered intelligence will take the switches control.

When it start it should do:

- Set the charger registers for safe use, with low/none charging current to protect the USB from overcurrent
- Open switch 2
- Close switch 1
- Set the charger to charge, now that it is the only power consumer

My testing till now made me think the charger stays on as low as it has power (possible battery) but only turns on, on the adapter power. Is this correct?

THANK YOU!!!

Part Number:DAC37J84

My FPGA platform is KCU105, which has one HPC and one LPC FMC interface. My HPC has been used. So Can the DAC37J84 be interfaced to LPC?

I checked the DAC37J84 and it showed the FMC was CON_SMVT_40x10_ASP-134487-01. And I checked the KCU 105 and it showed the FMC was Samtec ASP_134603_01.  So can they be connected directly?

Part Number:TPS24710

Hi,

Could you please tell me how to change the start-up delay and the ramp-up time when pulling EN pin to high during the power-on as the following timing chart ?
We would like to decrease the start-up delay and increase the ramp-up time ?
In addition, please share me if you have the application note regarding the additional circuit.

Best regards,
Kato

Part Number:TCAN1042HG

Hi team,

I want to check how to get the TCAN FD function with the device TCAN1042HG? What's the difference between the normal function and FD mode for the MCU side about the software? Thanks.

BR

Frank

Part Number:PROCESSOR-SDK-AM335X

Tool/software: Linux

Hello,

we activated the 'Fully Preemptible Kernel (RT)'  mode in our linux config and have now the issue that the process [ksoftirqd/0] has always high CPU load and blocks the system.

We use the Linux USB Gadget functionality and the problem is more reproducable when a USB connection is available.

Our System:

CPU: TI AM335X

repository: git://git.ti.com/processor-sdk/processor-sdk-linux.git

branch: processor-sdk-linux-rt-03.03.00

Do you know some problems with the preembtion and the ksoftirqd/0?

What can be the cause, that the ksoftirqd/0 has a high cpu load?

Thanks in advance

Regards,

Christian Fisahn

Part Number:CC3100MOD

Hi,

Does the modules support non OS - SPI support? for general ARM processor, 

Best Regards,

Umamahesh

Hi,

I am working on a project to trigger (on and off) the battery wirelessly to release the current from it at User choice. For instance, I have an implantable device inside the body and the idea is to trigger the battery wirelessly (at particular frequency) using the Remote Control at user hand.  The wireless communication between the user remote control and implant is facilitated by implantable and user antennas as shown in attached figure. 

I am interested to release the current at user choice in pulsatile manner. I have a proposed setup in my mind as in attached figure. Where the sensor is actuated by a particular frequency and then instructs the controlling circuit to actuate the battery for releasing current towards the Device.

I need to know the possible ways to complete the task. Does TI has any reference designs for such particular task ?

Looking forward to hear from you soon.

Thanks and Best Regards

Part Number:IWR1642

I take IWR1642 outdoor tests and find some signal quality issue, please see the pictures below.

parameters: PRT = 27us, idle time 2us, adc st time 4us, sampling rate 6.25Msps, ramp time 25us, tx st time 0us, slope rate 5.5MHz/us， AGC gain 36

I found peaks across the doppler dimension, and it varies between different antennas. It seems RF problem, but I don't know why.

Part Number:TMS320C6748

Tool/software: Code Composer Studio

Hi,

I am developing an audio processor using the LCDK and am currently attempting to implement an echo effect within my system. I am using the McASP Staterware example as a barebones code and adding my own code on top of it. I have successfully implemented an echo effect through the use of arrays, by storing previous rxBuf values and replaying them after a given period.

My problem is, that the rxBuf data contains a noticeable amount of noise. The noise seems to arise when copying the buffer values to a variable (for manipulation) and back again. Could anyone advise me on how to either remove the noise, or how to manipulate the buffer data more cleanly.

/**
 * \file  mcaspPlayBk.c
 *
 * \brief Sample application for McASP. This application loops back the input
 *        at LINE_IN of the EVM to the LINE_OUT of the EVM. 
 */

/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 
*
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

#include "edma_event.h" 
#include "interrupt.h"
#include "soc_C6748.h"
#include "hw_syscfg0_C6748.h"
#include "lcdkC6748.h"
#include "codecif.h"
#include "mcasp.h"
#include "aic31.h"
#include "edma.h"
#include "psc.h"

#include <math.h>
#include <string.h>

/******************************************************************************
**                      INTERNAL MACRO DEFINITIONS
******************************************************************************/
/*
** Values which are configurable
*/
/* Slot size to send/receive data */
#define SLOT_SIZE                             (16u)

/* Word size to send/receive data. Word size <= Slot size */
#define WORD_SIZE                             (16u)

/* Sampling Rate which will be used by both transmit and receive sections */
#define SAMPLING_RATE                         (48000u)

/* Number of channels, L & R */
#define NUM_I2S_CHANNELS                      (2u) 

/* Number of samples to be used per audio buffer */
#define NUM_SAMPLES_PER_AUDIO_BUF             (24000u)

/* Number of buffers used per tx/rx */
#define NUM_BUF                               (3u)

/* Number of linked parameter set used per tx/rx */
#define NUM_PAR                               (2u)

/* Specify where the parameter set starting is */
#define PAR_ID_START                          (40u)

/* Number of samples in loop buffer */
#define NUM_SAMPLES_LOOP_BUF                  (10u)

/* AIC3106 codec address */
#define I2C_SLAVE_CODEC_AIC31                 (0x18u) 

/* Interrupt channels to map in AINTC */
#define INT_CHANNEL_I2C                       (2u)
#define INT_CHANNEL_MCASP                     (2u)
#define INT_CHANNEL_EDMACC                    (2u)

/* McASP Serializer for Receive */
#define MCASP_XSER_RX                         (14u)

/* McASP Serializer for Transmit */
#define MCASP_XSER_TX                         (13u)

/*
** Below Macros are calculated based on the above inputs
*/
#define NUM_TX_SERIALIZERS                    ((NUM_I2S_CHANNELS >> 1) \
                                               + (NUM_I2S_CHANNELS & 0x01))
#define NUM_RX_SERIALIZERS                    ((NUM_I2S_CHANNELS >> 1) \
                                               + (NUM_I2S_CHANNELS & 0x01))
#define I2S_SLOTS                             ((1 << NUM_I2S_CHANNELS) - 1)

#define BYTES_PER_SAMPLE                      ((WORD_SIZE >> 3) \
                                               * NUM_I2S_CHANNELS)

#define AUDIO_BUF_SIZE                        (NUM_SAMPLES_PER_AUDIO_BUF \
                                               * BYTES_PER_SAMPLE)

#define TX_DMA_INT_ENABLE                     (EDMA3CC_OPT_TCC_SET(1) | (1 \
                                               << EDMA3CC_OPT_TCINTEN_SHIFT))
#define RX_DMA_INT_ENABLE                     (EDMA3CC_OPT_TCC_SET(0) | (1 \
                                               << EDMA3CC_OPT_TCINTEN_SHIFT))

#define PAR_RX_START                          (PAR_ID_START)
#define PAR_TX_START                          (PAR_RX_START + NUM_PAR)

/*
** Definitions which are not configurable 
*/
#define SIZE_PARAMSET                         (32u)
#define OPT_FIFO_WIDTH                        (0x02 << 8u)

/******************************************************************************
**                      INTERNAL FUNCTION PROTOTYPES
******************************************************************************/
static void McASPErrorIsr(void);
static void McASPErrorIntSetup(void);
static void AIC31I2SConfigure(void);
static void McASPI2SConfigure(void);
static void McASPTxDMAComplHandler(void);
static void McASPRxDMAComplHandler(void);
static void EDMA3CCComplIsr(void);
static void I2SDataTxRxActivate(void);
static void I2SDMAParamInit(void);
static void ParamTxLoopJobSet(unsigned short parId);
static void BufferTxDMAActivate(unsigned int txBuf, unsigned short numSamples,
                                unsigned short parToUpdate, 
                                unsigned short linkAddr);
static void BufferRxDMAActivate(unsigned int rxBuf, unsigned short parId,
                                unsigned short parLink);

/******************************************************************************
**                      INTERNAL VARIABLE DEFINITIONS
******************************************************************************/
static unsigned char loopBuf[NUM_SAMPLES_LOOP_BUF * BYTES_PER_SAMPLE] = {0};

/*
** Transmit buffers. If any new buffer is to be added, define it here and 
** update the NUM_BUF.
*/
signed char txBuf0[AUDIO_BUF_SIZE];
signed char txBuf1[AUDIO_BUF_SIZE];
signed char txBuf2[AUDIO_BUF_SIZE];

/*
** Receive buffers. If any new buffer is to be added, define it here and 
** update the NUM_BUF.
*/
signed char rxBuf0[AUDIO_BUF_SIZE];
signed char rxBuf1[AUDIO_BUF_SIZE];
signed char rxBuf2[AUDIO_BUF_SIZE];

/*
** Next buffer to receive data. The data will be received in this buffer.
*/
static volatile unsigned int nxtBufToRcv = 0;

/*
** The RX buffer which filled latest.
*/
static volatile unsigned int lastFullRxBuf = 0;

/*
** The PX buffer which filled latest.
*/
static volatile unsigned int lastFullPxBuf = NUM_BUF - 1;

/*
** The offset of the paRAM ID, from the starting of the paRAM set.
*/
static volatile unsigned short parOffRcvd = 0;

/*
** The offset of the paRAM ID sent, from starting of the paRAM set.
*/
static volatile unsigned short parOffSent = 0;

/*
** The offset of the paRAM ID to be sent next, from starting of the paRAM set. 
*/
static volatile unsigned short parOffTxToSend = 0;

/*
** The transmit buffer which was sent last.
*/
static volatile unsigned int lastSentTxBuf = NUM_BUF - 1;

/******************************************************************************
**                      INTERNAL CONSTATNT DEFINITIONS
******************************************************************************/
/* Array of receive buffer pointers */
signed int rxBufPtr[NUM_BUF] =
       { 
           (signed int) rxBuf0,
           (signed int) rxBuf1,
           (signed int) rxBuf2
       };

/* Array of transmit buffer pointers */
signed int txBufPtr[NUM_BUF] =
       { 
           (signed int) txBuf0,
           (signed int) txBuf1,
           (signed int) txBuf2
       };

/*
** Default paRAM for Transmit section. This will be transmitting from 
** a loop buffer.
*/
static struct EDMA3CCPaRAMEntry const txDefaultPar = 
       {
           (unsigned int)(EDMA3CC_OPT_DAM  | (0x02 << 8u)), /* Opt field */
           (unsigned int)loopBuf, /* source address */
           (unsigned short)(BYTES_PER_SAMPLE), /* aCnt */
           (unsigned short)(NUM_SAMPLES_LOOP_BUF), /* bCnt */ 
           (unsigned int) SOC_MCASP_0_DATA_REGS, /* dest address */
           (short) (BYTES_PER_SAMPLE), /* source bIdx */
           (short)(0), /* dest bIdx */
           (unsigned short)(PAR_TX_START * SIZE_PARAMSET), /* link address */
           (unsigned short)(0), /* bCnt reload value */
           (short)(0), /* source cIdx */
           (short)(0), /* dest cIdx */
           (unsigned short)1 /* cCnt */
       };

/*
** Default paRAM for Receive section.  
*/
static struct EDMA3CCPaRAMEntry const rxDefaultPar =
       {
           (unsigned int)(EDMA3CC_OPT_SAM  | (0x02 << 8u)), /* Opt field */
           (unsigned int)SOC_MCASP_0_DATA_REGS, /* source address */
           (unsigned short)(BYTES_PER_SAMPLE), /* aCnt */
           (unsigned short)(1), /* bCnt */
           (unsigned int)rxBuf0, /* dest address */
           (short) (0), /* source bIdx */
           (short)(BYTES_PER_SAMPLE), /* dest bIdx */
           (unsigned short)(PAR_RX_START * SIZE_PARAMSET), /* link address */
           (unsigned short)(0), /* bCnt reload value */
           (short)(0), /* source cIdx */
           (short)(0), /* dest cIdx */
           (unsigned short)1 /* cCnt */
       };

/******************************************************************************
**                          FUNCTION DEFINITIONS
******************************************************************************/
/*
** Assigns loop job for a parameter set
*/
static void ParamTxLoopJobSet(unsigned short parId)
{
    EDMA3CCPaRAMEntry paramSet;
    
    memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
  
    /* link the paRAM to itself */
    paramSet.linkAddr = parId * SIZE_PARAMSET;

    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, parId, &paramSet);
}

/*
** Initializes the DMA parameters.
** The RX basic paRAM set(channel) is 0 and TX basic paRAM set (channel) is 1.
**
** The RX paRAM set 0 will be initialized to receive data in the rx buffer 0.
** The transfer completion interrupt will not be enabled for paRAM set 0;
** paRAM set 0 will be linked to linked paRAM set starting (PAR_RX_START) of RX.
** and further reception only happens via linked paRAM set. 
** For example, if the PAR_RX_START value is 40, and the number of paRAMS is 2, 
** reception paRAM set linking will be initialized as 0-->40-->41-->40
**
** The TX paRAM sets will be initialized to transmit from the loop buffer.
** The size of the loop buffer can be configured.   
** The transfer completion interrupt will not be enabled for paRAM set 1;
** paRAM set 1 will be linked to linked paRAM set starting (PAR_TX_START) of TX.
** All other paRAM sets will be linked to itself.
** and further transmission only happens via linked paRAM set.
** For example, if the PAR_RX_START value is 42, and the number of paRAMS is 2, 
** So transmission paRAM set linking will be initialized as 1-->42-->42, 43->43. 
*/
static void I2SDMAParamInit(void)
{
    EDMA3CCPaRAMEntry paramSet;
    int idx; 
 
    /* Initialize the 0th paRAM set for receive */ 
    memcpy(&paramSet, &rxDefaultPar, SIZE_PARAMSET - 2);

    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, &paramSet);

    /* further paramsets, enable interrupt */
    paramSet.opt |= RX_DMA_INT_ENABLE; 
 
    for(idx = 0 ; idx < NUM_PAR; idx++)
    {
        paramSet.destAddr = rxBufPtr[idx];

        paramSet.linkAddr = (PAR_RX_START + ((idx + 1) % NUM_PAR)) 
                             * (SIZE_PARAMSET);        

        paramSet.bCnt =  NUM_SAMPLES_PER_AUDIO_BUF;

        /* 
        ** for the first linked paRAM set, start receiving the second
        ** sample only since the first sample is already received in
        ** rx buffer 0 itself.
        */
        if( 0 == idx)
        {
            paramSet.destAddr += BYTES_PER_SAMPLE;
            paramSet.bCnt -= BYTES_PER_SAMPLE;
        }

        EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, (PAR_RX_START + idx), &paramSet);
    } 

    /* Initialize the required variables for reception */
    nxtBufToRcv = idx % NUM_BUF;
    lastFullRxBuf = NUM_BUF - 1;
    parOffRcvd = 0;

    /* Initialize the 1st paRAM set for transmit */ 
    memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET);

    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX, &paramSet);

    /* rest of the params, enable loop job */
    for(idx = 0 ; idx < NUM_PAR; idx++)
    {
        ParamTxLoopJobSet(PAR_TX_START + idx);
    }
 
    /* Initialize the variables for transmit */
    parOffSent = 0;
    lastSentTxBuf = NUM_BUF - 1; 
}

/*
** Function to configure the codec for I2S mode
*/
static void AIC31I2SConfigure(void)
{
    volatile unsigned int delay = 0xFFF;

    AIC31Reset(SOC_I2C_0_REGS);
    while(delay--);

    /* Configure the data format and sampling rate */
    AIC31DataConfig(SOC_I2C_0_REGS, AIC31_DATATYPE_I2S, SLOT_SIZE, 0);
    AIC31SampleRateConfig(SOC_I2C_0_REGS, AIC31_MODE_BOTH, SAMPLING_RATE);

    /* Initialize both ADC and DAC */
    AIC31ADCInit(SOC_I2C_0_REGS);
    AIC31DACInit(SOC_I2C_0_REGS);
}

/*
** Configures the McASP Transmit Section in I2S mode.
*/
static void McASPI2SConfigure(void)
{
    McASPRxReset(SOC_MCASP_0_CTRL_REGS);
    McASPTxReset(SOC_MCASP_0_CTRL_REGS);

    /* Enable the FIFOs for DMA transfer */
    McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
    McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

    /* Set I2S format in the transmitter/receiver format units */
    McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
                     MCASP_RX_MODE_DMA);
    McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
                     MCASP_TX_MODE_DMA);

    /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
    McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 
                        MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
    McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 
                        MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);

    /* configure the clock for receiver */
    McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
    McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 
    McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
                          0x00, 0xFF);

    /* configure the clock for transmitter */
    McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
    McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 
    McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
                          0x00, 0xFF);
 
    /* Enable synchronization of RX and TX sections  */  
    McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

    /* Enable the transmitter/receiver slots. I2S uses 2 slots */
    McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
    McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

    /*
    ** Set the serializers, Currently only one serializer is set as
    ** transmitter and one serializer as receiver.
    */
    McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
    McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

    /*
    ** Configure the McASP pins 
    ** Input - Frame Sync, Clock and Serializer Rx
    ** Output - Serializer Tx is connected to the input of the codec 
    */
    McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
    McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AXR(MCASP_XSER_TX));
    McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX 
                                               | MCASP_PIN_ACLKX
                                               | MCASP_PIN_AFSR
                                               | MCASP_PIN_ACLKR
                                               | MCASP_PIN_AXR(MCASP_XSER_RX));

    /* Enable error interrupts for McASP */
    McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 
                                            | MCASP_TX_CLKFAIL 
                                            | MCASP_TX_SYNCERROR
                                            | MCASP_TX_UNDERRUN);

    McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 
                                            | MCASP_RX_CLKFAIL
                                            | MCASP_RX_SYNCERROR 
                                            | MCASP_RX_OVERRUN);
}

/*
** Sets up the interrupts for EDMA in AINTC
*/
static void EDMA3IntSetup(void)
{
#ifdef _TMS320C6X
    IntRegister(C674X_MASK_INT5, EDMA3CCComplIsr);
    IntEventMap(C674X_MASK_INT5, SYS_INT_EDMA3_0_CC0_INT1);
    IntEnable(C674X_MASK_INT5);
#else
    IntRegister(SYS_INT_CCINT0, EDMA3CCComplIsr);
    IntChannelSet(SYS_INT_CCINT0, INT_CHANNEL_EDMACC); 
    IntSystemEnable(SYS_INT_CCINT0);
#endif
}

/*
** Sets up the error interrupts for McASP in AINTC
*/
static void McASPErrorIntSetup(void)
{
#ifdef _TMS320C6X
    IntRegister(C674X_MASK_INT6, McASPErrorIsr);
    IntEventMap(C674X_MASK_INT6, SYS_INT_MCASP0_INT);
    IntEnable(C674X_MASK_INT6);
#else
    /* Register the error ISR for McASP */
    IntRegister(SYS_INT_MCASPINT, McASPErrorIsr);

    IntChannelSet(SYS_INT_MCASPINT, INT_CHANNEL_MCASP);
    IntSystemEnable(SYS_INT_MCASPINT);
#endif
}

/*
** Activates the data transmission/reception
** The DMA parameters shall be ready before calling this function.
*/
static void I2SDataTxRxActivate(void)
{
    /* Start the clocks */
    McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
    McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);

    /* Enable EDMA for the transfer */
    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
                        EDMA3_TRIG_MODE_EVENT);
    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 
                        EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

    /* Activate the  serializers */
    McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
    McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

    /* make sure that the XDATA bit is cleared to zero */
    while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

    /* Activate the state machines */
    McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
    McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

/*
** Activates the DMA transfer for a parameterset from the given buffer.
*/
void BufferTxDMAActivate(unsigned int txBuf, unsigned short numSamples,
                         unsigned short parId, unsigned short linkPar)
{
    EDMA3CCPaRAMEntry paramSet;

    /* Copy the default paramset */
    memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
    
    /* Enable completion interrupt */
    paramSet.opt |= TX_DMA_INT_ENABLE;
    paramSet.srcAddr =  txBufPtr[txBuf];
    paramSet.linkAddr = linkPar * SIZE_PARAMSET;  
    paramSet.bCnt = numSamples;

    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, parId, &paramSet);
}

/*
** The main function. Application starts here.
*/

int i, x = 0, y = 0, w = 0, z = 0, v = 0;
signed int Echo1[2 * NUM_SAMPLES_PER_AUDIO_BUF] = {0}; // all elements 0
signed int Echo2[2 * NUM_SAMPLES_PER_AUDIO_BUF] = {0}; // all elements 0
signed int Echo3[2 * NUM_SAMPLES_PER_AUDIO_BUF] = {0}; // all elements 0
signed int Echo4[2 * NUM_SAMPLES_PER_AUDIO_BUF] = {0}; // all elements 0

int main(void)
{
    printf("Audio Buf (bytes): %u\n", AUDIO_BUF_SIZE);
    unsigned short parToSend;
    unsigned short parToLink;

    /* Set up pin mux for I2C module 0 */
    I2CPinMuxSetup(0);
    McASPPinMuxSetup();

    /* Power up the McASP module */
    PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_MCASP0, PSC_POWERDOMAIN_ALWAYS_ON,
             PSC_MDCTL_NEXT_ENABLE);

    /* Power up EDMA3CC_0 and EDMA3TC_0 */
    PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_CC0, PSC_POWERDOMAIN_ALWAYS_ON,
             PSC_MDCTL_NEXT_ENABLE);
    PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC0, PSC_POWERDOMAIN_ALWAYS_ON,
             PSC_MDCTL_NEXT_ENABLE);

#ifdef _TMS320C6X
    // Initialize the DSP interrupt controller
    IntDSPINTCInit();
#else
    /* Initialize the ARM Interrupt Controller.*/
    IntAINTCInit();
#endif

    /* Initialize the I2C 0 interface for the codec AIC31 */
    I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C, I2C_SLAVE_CODEC_AIC31);

    EDMA3Init(SOC_EDMA30CC_0_REGS, 0);
    EDMA3IntSetup(); 

    McASPErrorIntSetup();
  
#ifdef _TMS320C6X
    IntGlobalEnable();
#else
    /* Enable the interrupts generation at global level */ 
    IntMasterIRQEnable();
    IntGlobalEnable();
    IntIRQEnable();
#endif

    /*
    ** Request EDMA channels. Channel 0 is used for reception and
    ** Channel 1 is used for transmission
    */
    EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
                        EDMA3_CHA_MCASP0_TX, EDMA3_CHA_MCASP0_TX, 0);
    EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
                        EDMA3_CHA_MCASP0_RX, EDMA3_CHA_MCASP0_RX, 0);

    /* Initialize the DMA parameters */
    I2SDMAParamInit();

    /* Configure the Codec for I2S mode */
    AIC31I2SConfigure();

    /* Configure the McASP for I2S */
    McASPI2SConfigure();
  
    /* Activate the audio transmission and reception */ 
    I2SDataTxRxActivate();
   
    /*
    ** Loop forever. if a new buffer is received, the lastFullRxBuf will be
    ** updated in the rx completion ISR. if it is not the lastSentTxBuf, 
    ** buffer is to be sent. This has to be mapped to proper paRAM set.
    */

    while(1)
    {
        Echo1[0] = 0;
        Echo2[0] = 0;
        Echo3[0] = 0;
        Echo4[0] = 0;

        Echo1[NUM_SAMPLES_PER_AUDIO_BUF] = 0;
        Echo2[NUM_SAMPLES_PER_AUDIO_BUF] = 0;
        Echo3[NUM_SAMPLES_PER_AUDIO_BUF] = 0;
        Echo4[NUM_SAMPLES_PER_AUDIO_BUF] = 0;

        if(lastFullRxBuf != lastSentTxBuf)
        {  
            /*
            ** Start the transmission from the link paramset. The param set 
            ** 1 will be linked to param set at PAR_TX_START. So do not 
            ** update paRAM set1.
            */ 
            parToSend =  PAR_TX_START + (parOffTxToSend % NUM_PAR);
            parOffTxToSend = (parOffTxToSend + 1) % NUM_PAR;
            parToLink  = PAR_TX_START + parOffTxToSend; 

            lastSentTxBuf = (lastSentTxBuf + 1) % NUM_BUF;

            for(i = 4; i <= AUDIO_BUF_SIZE; i += 4)     // AUDIO_BUF_SIZE = 96000  // NUM_SAMPLES_PER_AUDIO_BUF = 24000
            {
                z = 0;
                if (lastSentTxBuf == 0) {
                    z = rxBuf0[i] + (rxBuf0[i+1] << 8);
                    Echo4[(i/4)] = Echo3[(i/4)];
                    Echo3[(i/4)] = Echo2[(i/4)];
                    Echo2[(i/4)] = Echo1[(i/4)];
                    Echo1[(i/4)] = z;
                    v = z/5 + Echo1[(i/4)+1]/5 + Echo2[(i/4)+1]/5 + Echo3[(i/4)+1]/5 + Echo4[(i/4)+1]/5;
                    rxBuf0[i-4] = v;
                    rxBuf0[i-3] = v >> 8;
                }
                else if (lastSentTxBuf == 1) {
                    z = rxBuf0[i] + (rxBuf0[i+1] << 8);
                    Echo4[(i/4)] = Echo3[(i/4)];
                    Echo3[(i/4)] = Echo2[(i/4)];
                    Echo2[(i/4)] = Echo1[(i/4)];
                    Echo1[(i/4)] = z;
                    v = z/5 + Echo1[(i/4)+1]/5 + Echo2[(i/4)+1]/5 + Echo3[(i/4)+1]/5 + Echo4[(i/4)+1]/5;
                    rxBuf1[i-4] = v;
                    rxBuf1[i-3] = v >> 8;
                }
                else if (lastSentTxBuf == 2) {
                    z = rxBuf0[i] + (rxBuf0[i+1] << 8);
                    Echo4[(i/4)] = Echo3[(i/4)];
                    Echo3[(i/4)] = Echo2[(i/4)];
                    Echo2[(i/4)] = Echo1[(i/4)];
                    Echo1[(i/4)] = z;
                    v = z/5 + Echo1[(i/4)+1]/5 + Echo2[(i/4)+1]/5 + Echo3[(i/4)+1]/5 + Echo4[(i/4)+1]/5;
                    rxBuf2[i-4] = v;
                    rxBuf2[i-3] = v >> 8;
                }
            }

            /* Copy the buffer */
            memcpy((void *)txBufPtr[lastSentTxBuf],
                   (void *)rxBufPtr[lastFullRxBuf],
                   AUDIO_BUF_SIZE);

            /*
            ** Send the buffer by setting the DMA params accordingly.
            ** Here the buffer to send and number of samples are passed as
            ** parameters. This is important, if only transmit section 
            ** is to be used.
            */
            BufferTxDMAActivate(lastSentTxBuf, NUM_SAMPLES_PER_AUDIO_BUF,
                                (unsigned short)parToSend,
                                (unsigned short)parToLink);
        }
    }
}  

/*
** Activates the DMA transfer for a parameter set from the given buffer.
*/
static void BufferRxDMAActivate(unsigned int rxBuf, unsigned short parId,
                                unsigned short parLink)
{
    EDMA3CCPaRAMEntry paramSet;

    /* Copy the default paramset */
    memcpy(&paramSet, &rxDefaultPar, SIZE_PARAMSET - 2);

    /* Enable completion interrupt */
    paramSet.opt |= RX_DMA_INT_ENABLE;
    paramSet.destAddr =  rxBufPtr[rxBuf];
    paramSet.bCnt =  NUM_SAMPLES_PER_AUDIO_BUF;
    paramSet.linkAddr = parLink * SIZE_PARAMSET ;

    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, parId, &paramSet);
}

/*
** This function will be called once receive DMA is completed
*/
static void McASPRxDMAComplHandler(void)
{
    unsigned short nxtParToUpdate;

    /*
    ** Update lastFullRxBuf to indicate a new buffer reception
    ** is completed.
    */
    lastFullRxBuf = (lastFullRxBuf + 1) % NUM_BUF;
    nxtParToUpdate =  PAR_RX_START + parOffRcvd;  
    parOffRcvd = (parOffRcvd + 1) % NUM_PAR;
 
    /*
    ** Update the DMA parameters for the received buffer to receive
    ** further data in proper buffer
    */
    BufferRxDMAActivate(nxtBufToRcv, nxtParToUpdate,
                        PAR_RX_START + parOffRcvd);
    
    /* update the next buffer to receive data */ 
    nxtBufToRcv = (nxtBufToRcv + 1) % NUM_BUF;
}

/*
** This function will be called once transmit DMA is completed
*/
static void McASPTxDMAComplHandler(void)
{
    ParamTxLoopJobSet((unsigned short)(PAR_TX_START + parOffSent));

    parOffSent = (parOffSent + 1) % NUM_PAR;
}

/*
** EDMA transfer completion ISR
*/
static void EDMA3CCComplIsr(void) 
{ 
#ifdef _TMS320C6X
    IntEventClear(SYS_INT_EDMA3_0_CC0_INT1);
#else
    IntSystemStatusClear(SYS_INT_CCINT0);
#endif

    /* Check if receive DMA completed */
    if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_RX)) 
    { 
        /* Clear the interrupt status for the 0th channel */
        EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX); 
        McASPRxDMAComplHandler();
    }
    
    /* Check if transmit DMA completed */
    if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_TX)) 
    { 
        /* Clear the interrupt status for the first channel */
        EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX); 
        McASPTxDMAComplHandler();
    }
}

/*
** Error ISR for McASP
*/
static void McASPErrorIsr(void)
{
#ifdef _TMS320C6X
    IntEventClear(SYS_INT_MCASP0_INT);
#else
    IntSystemStatusClear(SYS_INT_MCASPINT);
#endif

    ; /* Perform any error handling here.*/
}

/***************************** End Of File ***********************************/

Part Number:BQ76PL536A

I am trying to understand how to convert the raw ratiometric value (which I understand is a voltage ) from the BQ temperature registers/output to a value in degrees.

I found the code for SLAA478 but it does not do any such conversion. I am using the Panasonic NTC thermistor recommended on the datasheet. 

Part Number:XTR101

Hello,

I am firmware engineer and want to develop voltage to current (4-20mA) converter for my temperature monitoring project. I have identified 2-wire PT100 and XTR101 for this project.

I have very less experience in PCB design. There are no XTR101 reference design files in TI product website.

Can anyone send XTR101 reference design files (schematics and PCB)? 

Part Number:RF430FRL152H

Tool/software: Code Composer Studio

I've been playing around with the RF430FRL152HEVM for a while now along with going as far as building an RF programmer on a breakout for new RF430FRL152H.  I am now getting to the point where I need to start thinking about actual device code and what the best options are for programming the device down the road.  What exactly is missed when using over the air programming vs. programming through JTAG and CCS.  

http://www.ti.com/lit/ug/slau607b/slau607b.pdf it can program is F867h to FFFFh."  

Taking a look at http://www.ti.com/lit/ug/slau603b/slau603b.pdf , on page 33 we get register information starting at F868h to F8B0h (along with any offsets to account for additional logging space).  These registers appear to be only related to the SD14 settings along with the General Control and Firmware Status Registers.  

On the other hand, http://www.ti.com/lit/ug/slau506/slau506.pdf in Table 9-3 for the largest configuration available. The base address can be found in the device-specific data sheet."  However, in the device specific data sheet, http://www.ti.com/lit/ds/symlink/rf430frl152h.pdf, 

have no idea what some of these registers are.  Starting from the top:

Write succeeded at block: 0 at address: F868h

Write succeeded at block: 3 at address: F880h

Write succeeded at block: 6 at address: F898h

These fall within the F868h to F8B0h range that the data sheet says the OTA has access to program.  Then you get into the rest

Write succeeded at block: 9 at address: F8B0h
Write succeeded at block: 12 at address: F8C8h
Write succeeded at block: 15 at address: F8E0h
Write succeeded at block: 18 at address: F8F8h

Plus many others.  This all appears to fall into the Logging FRAM Memory Space, but obviously is part of the original program.  

So long story short, it looks like all over the air should have access to are registers handling the SD14 captures, but it looks like the programmer is programming much more into FRAM space that does not seem to have any information as to what it is.