Part Number:66AK2H12
Hi,
Thanks to supporters in forum, our project keeps going on. Thanks a lot.
Currently, I focused on EMIF operation on our platform (66ak2h12 inside our specific board)
We used CE1 space(0x34000000) for communication, and HW(FPGA) tried to access that area.
But some weird operation is observed. When DSP writes 16bit data on CE1 space, HW catches the 32 bit data.
test process)
1. Add EMIF initialization code on gel script.(Actually, we didn`t use NOR/NAND flash. so I didn`t initialize the NOR/NAND related register)
2. Add test script on gel script as a hotemu function. So We can test it as we want.
3. chipscope is attached on FPGA. When the signal is received on FPGA, it can analysis it(datasize, contents of data, write enable signal etc)
our code snippets are below:
initialization :
EMIF_Init()
{
GEL_TextOut("Revision = %x \n",,,,,EMIF_RCSR);
GEL_TextOut("EMIF Initiated\n");
// W_SETUP = 0x3, W_STROBE = 0x7, W_HOLD = 0x1
// R_SETUP = 0x3, R_STROBE = 0xF, R_HOLD = 0x1
// Data bus : 16bit
EMIF_A2CR = 0x0C72679D;
GEL_TextOut("EMIF Init Done\n");
}Test code :
hotmenu EMIF_Test()
{
*(unsigned short*)(0x34000018) = (unsigned short)0x1234; // for testing 16 bit data
//*(unsigned short*)(0x34000010) = 0x12345678;
//*(unsigned short*)(0x34000020) = 3;
}expected result : FPGA receive the 0x1234(16bit)
observed result : FPGA receive the 0x00001234(32bit) <- FPGA received two write enable signal and get data(0x1234 and 0x0000)
Is this the right operation of EMIF? or should I consider something at other side?
Thanks in advance.
Chanseok
