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optimizing C66x PCIe transfers for multiple cores

January 9, 2014, 4:47 pm
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Vivek and other TI experts-

With the quad 6678 PCIe card, we're using memcpy to/from host-mapped memory and DDR3 mem.  Typically we get a rate of around 90 Mbyte/sec.  However when code is running concurrently on multiple cores, rates drop substantially.  Is c66x side EDMA the only method to maintain higher throughput?  Here are some additional notes / questions:

  -DDR3 mem areas we assign to each core are marked as non-cacheable

  -does spacing between sections of DDR3 mem assigned to each core have any effect (i.e. something like a "bank" effect) ?

  -from the documentation we understand all memcpy's are outbound transactions.  We also have some inbound (host-initiated) transactions occcurring that compete for PCIe bus bandwidth.  Would EDMA help substantially with this, or should we find a way to make all transactions either inbound or outbound?

We can provide our transfer rate lab measurements if needed.  Thanks.

-Jeff
Signalogic

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ADC with MSP430G2553

December 16, 2013, 12:50 am
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Hi everybody;
I’m a beginner; before starting this thread, I’ve read many others regarding ADC in this forum, but I’d like to have your comments about the circuit I’m working on.

1)      The microcontroller is the MSP430G2553 (in TSSOP package), decoupled with the “0,1μF + 10μF combo” capacitors.

2)      The supply voltage comes from an LDO (2.5V), properly decoupled.

3)      The source of the analog input is the output of an OpAmp; as written in its datasheet, “The output pins are low-impedance voltage sources”.

4)      I’ve placed a low-pass filter BEFORE the OpAmp, and I’ve properly decoupled the OpAmp. The VCC pin of the OpAmp is directly connected to a generic pin of the microcontroller, which turns ON the OpAmp when needed.

You can see the microcontroller + LDO in the picture below.
Question #1: in order to have a better ADC reading, would it be better using a different ground trace for the MCU and the LDO, like in the picture below?
However, with the scheme as shown in the first picture, I’m having very good results, until I don’t  do anything else than reading the ADC  value.
But if I try to do something else (even just starting a timer, or lighting a led), results begin to deteriorate.
I thought the problem was that I didn’t place a decoupling capacitor close to the pin that receives the analog signal, but as  Jens-Michael Gross wrote in this thread
“The internal cap and its 1k series resistor is a low-pass filter. An external cap with the signal source impedance is a low-pass too. The lower one of the two defines the characteristic of the signal the ADC 'sees'.”
Considering that in my application the source impedance should be low, maybe that capacitor wouldn’t help.
So I begin to think that the problem is the fact that the MCU I’m using doesn’t have separate analog power pins (AVCC and AVSS). But the same MCU is available in QFN format, which has those pins.
Could it be the solution to my problem?
If so, should I use the following solution (Picture 3)?
I’ve placed a 10Ω resistor between AVCC and DVCC because I found it in many threads written by Jens-Michael Gross, and it makes sense. Considering that I’m using the analog supply voltage just for the ADC, maybe I could rise the value up to 100Ω.
Could it be the right solution?
Should I use the same AVSS ground line for the OpAmp?
Thanks in advance to everybody.
Marco
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Configuration of WMM AC queue parameters from user app

December 1, 2013, 10:48 pm
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Hello,

I am trying to find out a way or a tool (like IW or Iwconfig) that can help modify default AC queue parameters like CWmin, max from user level. Alternatively, can someone point me on how this can be achieved by developing own application or can we add this functionality into tools like iw?

I see from the source code of driver/mac8011, the WMM standard parameter values are configured by default.

In addition, how does client/station settings of WMM parameters on Access Point take effect on the client. Does it use any application software or nl80211/cfg80211 layers?

Thanks,

Kedar

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ISO1050 problem when not connected to CAN bus

January 12, 2014, 9:10 am
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Summary: I built a CAN-repeater module with isolation to connect two buses, labeled F and W in this application. The W side has an ISO1050 whereas the F side is connected directly to the CAN-repeater chip. With both buses connected and everything powered up, the repeater works fine. However, when I disconnect the W side CAN bus from the repeater, the F bus gets heavy errors or locks up. In this application, the secondary W bus will sometimes be disconnected and I can't clobber the F bus!

Suspected problem: Without other nodes on the bus pulling towards recessive, perhaps the ISO1050 is not returning promptly to recessive. That causes the repeater to echo effectively a bus collision onto the F side – killing the F bus.

Other details:
1) Plugging an un-powered node with terminator into the W side shows the same problem (the node must be powered up to avoid clobbering the F side)
2) Both sides have protection diodes and a common-mode choke for noise immunity.

Any suggestions ?
Thanks!
Best Regards, Dave

Schematic below (note no terminator installed on W side)

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NFC Interfacing with I.MX 6 & WiLink8

January 12, 2014, 12:56 pm
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Hello!

My customer would like to add NFC functionality to their defibrillator product. Their host processor is an I.MX 6 and they are also connecting this MPU to our WiLink 8 device.

I believe that it is certainly possible to interface an I.MX 6 with the TRF7970A due to 4-wire SPI communication support, however in doing so are there any guidelines that should be followed and/or things to watch out for when connecting this transceiver to a competitor part?

If instead, say the customer decided to interface the transceiver IC with a TI MSP430/RF430 which would connect to the I.MX 6 (if required). Would this reduce their integration effort albeit at the cost of an MCU?

 

I appreciate any support that can be provided!

Thanks,

Sean

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Problem: Start core of TMS570LS over JTAG access

January 10, 2014, 7:05 am
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Hy friends,
we have a problem to start the core of the TMS570LS.
We develop models for PCB manufacturers for testing and programming.

With our "VarioTAP model" we generate access to the respective CPU core via the JTAG interface.

Method:

    A small executable program is written (program download) and launched  
in the internal RAM.

    This IP then communicates with the VarioTap model.
   
With this process we implement with corresponding IPs for programming
INTERNAL / NOR / NAND / SPI Flash.

Status of the work:
    -We have access over ICEPick_C  to the CORTEX_A8 core.
    -After initialize IcePick (read Chip-ID) we reset the CPU over IcePick (set SysReset Bit).

    -Stop the CPU core is also OK.

    -We can see the Power-Reset- and the Sys- Reset-bit in register SYSESR.

    -We can write and read memory and can read and write registers.

    -After program download (IP)we init register 13 with the stack value of the IP.
    
   -Unfortunately, we can not by means of the R0 register the PC describe (over op-code = 0xE1A0F000) to start the loaded RAM program.

    -We see the removal of the stop bit in the DSCR register but the Program does not go.

    -A read of PC after stop the core bring the value of the R13 (stack value).

Hint:
    The internal flash is empty.

What we need to consider? Does it have something to do with the LockStep?

Who can help me.

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INA326 Instrumentation Amp - Error in functioning

January 8, 2014, 4:32 am
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Please refer the connections of INA326 which I did in circuit. Initially I have assembled this much circuit only to check the performance of INA 326 and it is working fine.

Now I have integrated power supply sections(IC- TPS 5430 and IC- LM 2830) and 4-20 mA section(IC- XTR 111) along with this INA 326. All sections are working fine except INA 326.

I have Gas sensor whose operating voltage is 2.4V. So my common mode voltage becomes 1.2V. The input signal to INA 326 is around 120-160mV and I have to amplify it over 0-5V range.

The reference input of INA 326 is adjusted by potentiometer(1k).When both the input terminals are at same potential, the output should be zero ideally (practically 50-60mV). But I am getting around 600 to 700 mV output when the bridge is balanced and that  output voltage is not changing as expected after unbalancing the bridge (by applying gas to gas sensor). There is very small change in output voltage.

 Kindly advise

Atul Bhakay

Please advice with your suggestions.(Please visit the site to view this file)

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SMPTE 296

January 9, 2014, 10:53 pm
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Hi,

I trying to interface omnivision sensor configured to generate 720p format frame at 30 frames per second with 48Mhz input to VP_CLKin0 & CLKIN1.

Can somebody specify the maximum input clock that needs to be given to VP_CLKin0 & CLKIN1 to capture 720p format frame in OMAPL13X

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Kernel does not start after upgrading keystone U-Boot

January 13, 2014, 1:29 pm
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Note: This is with K2 EVM 1.1

I've been using a version of the keystone U-Boot I grabbed around June 2013 (around the time of MCSDK mcsdk_linux_3_00_00_11) along with the ./images from a newer version of MCSDK (mcsdk_linux_3_00_03_15) and it has been starting the linux kernel just fine.

I decided to upgrade my version of U-boot and now the booting will not get past  Starting kernel ...

As a quick test if I flash the .gph that came with mcsdk_linux_3_00_03_15, standup a tftp server and run the default u-boot boot of ramfs, it feezes at Starting kernel ...

If I move back to my mcsdk_linux_3_00_00_11 directory, load the .gph that came with it, and do the same thing, the arago-console image boots just fine.

Is this somehow related to my EVM version?

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C Concatenation Operator (##) Error

January 13, 2014, 11:17 am
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Hi,

I am trying to get a macro working.  I didn't create the macro but it looks easy enough to debug.  This is what I am seeing:

Macro call:

    CSL_FINST(ECAP_Ptr->ECCTL1, ECAP_ECCTL1_FREE_SOFT, STOP );

Macro definitions:

    #define CSL_FINST(reg, PER_REG_FIELD, TOKEN)                                \
        CSL_FINS((reg), PER_REG_FIELD, CSL_##PER_REG_FIELD##_##TOKEN)

    #define CSL_FINS(reg, PER_REG_FIELD, val)                                   \
        ((reg) = ((reg) & ~CSL_##PER_REG_FIELD##_MASK))

I get a compiler error: #18 expected a ")".


Does anyone got an idea why it's giving me this weird error?

I noticed that it compiles when I changed it to:

    CSL_FINST(ECAP_Ptr->ECCTL1, ECAP_ECCTL1_FREE_SOFT_MASK, STOP );

It looks like it didn't like the second ## operator in the CSL_FINS macro. 

The code worked on the TI v7.3.1 C674x Compiler using CCS 5.1, but I am using the TI v7.4.1 Compiler on CCS 5.3 now.  Even if I changed it to the TI v7.3.1 it doesn't compile either.  Not sure if some compiler switches that are preventing it from compiling on my new build.

Thanks.

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RM46L852ZWTT Production Availability

January 10, 2014, 12:38 am
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Neither Mouser or Digikey has the production version of this part, just the "X" version.


Is TI shipping production versions?

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OPA2835 - looking for an opamp

January 11, 2014, 11:15 pm
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Hi,

I am looking for an opamp for low frequency (up to 1MHz) which can do the below operation.

I need two opamps in one package.

The OPA2835 is a candidate but I need feedback resistor above 10K while TI recommend 2K.

Please advise as if I can use higher RF value and if not please suggest for a replacement.

Thanks.

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Signing in to My.ti from www.ti.com

January 13, 2014, 1:32 pm
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Though I can sign into My.ti from my window 7 laptop, I cannot sign in using my desktop Window 8.1 All-in-one computer. I do not know what to do. Did anyone else had the same problem?

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V3P3OUT

January 13, 2014, 11:02 am
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The datasheets calls for a 0.47 uF bypass cap to gnd. on the V3P3OUT voltage reference output.  There is the same part on the EVM board.  The datasheet says this output can be used to create a Vref if desired.  Can this pin be a no-connect if I'm providing my own external Vref inputs, or is the bypass required for proper operation whether or not any load is tied to this output?  Thanks.  Tony

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LDC1000 sensor mechanics

January 13, 2014, 1:36 pm
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There seem to be a few missing details in the data sheet. First, I cannot get the frequency counter to run at tank frequencies of 25 -30 Khz, the count register is off by a factor of 4 to 10. Based on the formulas given to derive frequency from the 24 bit count data, I am guessing the counter counts up at 1/3 the external clock frequency for 'LDC response time' cycles of tank oscillation, and then holds that as the 24 bit frequency data. Is this correct ? there is no clear explanation in the data sheet. Are there situations where a better ( or only possible) frequency measurement requires a lower external clock frequency  than the 6 Mhz on the EVM ?

Second, is there an approximation for the ideal filter cap value or is cut and fit the only way to tune the LDO ? At 28 Khz, I tried 100 pF thru .05 uf in decade steps. At .01, the filter waveform was at 1 VAC amplitude, but I still had no good frequency counting .

And third, doesn't the approximation for the Rs => Rp transformation impose some limitations on the ratio of the tank L and C ?  Are there  limits to that ratio ? I tried a 3 mH coil with a .01 cap, for an oscillator frequency of about 28 Khz. I am inclined to try use a 500 pF cap but am concerned about having an "unbalanced" LC combination. 

On the surface, the chip is indeed amazing in its sensitivity to metal surface area and proximity. We are trying to sense  ferrous material flow rate, and although the chip looks very promising the data sheet does not seem to provide a lot more than a cookbook approach, and offers few alternatives when things aren't working or tools to evaluate margins of error for a final design .  Any answers out there ?

     

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Absolute beginner question on Bit-Banding and HWREGBITW

January 12, 2014, 11:56 pm
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Hi everyone,

I am a beginner to ARM programming and I'm having the hardest time understanding bit-banding! I have read the ARM document here: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/Behcjiic.html, but I still don't understand what is going on. Can someone please explain what bit-banding is in simple terms?

In addition, I do not understand what the HWREGBITW function from inc/hw_types.h does. Is it used to set a bit in the bit band region? If so, how does it work?

I apologize for such simple questions but I feel like I am making no progress in trying to understand this myself. Thanks in advance!

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Beaglebone+WT1835MOD kernel

December 17, 2013, 8:25 am
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Hello,

    I am using the pre-compiled images downloaded from here:

http://processors.wiki.ti.com/index.php/WL8_release_download_page

It works perfectly. I am also trying to generate the images from the source code following:

http://software-dl.ti.com/sitara_linux/esd/AM335xSDK/latest/index_FDS.html

http://www.ti.com/tool/linuxezsdk-am335x-wilink8

When I try to power up de lan: ifconfig wlan 0 up it shows Error: ifconfig: SIOCGIFFLAGS: No Such device

Could you send me the .config file for having the right setting to generate the working images?

Best Regards.

Francisco.

         

            

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How to start MSP430F2274 BSL via UART?

December 18, 2013, 7:53 am
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Hello my friends.

First, sorry for my bad english.

I'm using a CubieBoard2 ( http://cubieboard.org/2013/06/19/cubieboard2-is-here/ ) with Cubian ( a linux distribuition bases on Debian for cubieboard2, Cubieboard + Debian = Cubian) and a MSP430F2274 ( http://www.ti.com/product/msp430f2274 ), DA package, in another board.

The serial communication between the both boards is working fine. Just connect the required pins (TX, RX, VCC and GND) from MSP board to CubieBoard2 pins, connecting at 9600 bauds, 8 data bits, no parity and 1 stop bit.

I need to start the MSP BSL to upload a new firmware from Cubieboard2 to MSP430F2274, using the same UART.

I'd connected also the RST pin (pin 1) and TEST pin (pin 7) of MSP to another 2 pins into cubieboard2.

I wrote a C++ program (for cubie) for use these 2 pins of cubieboard to try to reset the MSP for start the BSL program, following the slau319g.pdf document, but I had no success.


I downloaded the slau319g.zip file also, but I saw another sequence for reset the MSP that I saw in the slau319g.pdf.

The program I made, opens the UART port using 9600 bauds, 8 data bits, even parity and 1 stop bit.

Following the slau319g.pdf, the sequence (item 1.3.1) is:

1 - Set RST and TEST to low (zero).

2 - Do some delay (I did 1ms).

3 - Set TEST to high (one), making the first positive transition.

4 - Do some delay (I did 1ms).

5 - Set TEST to low (one).

6 - Do some delay (I did 1ms).

7 - Set TEST to high (one), making the second positive transition.

8 - Do some delay (I did 1ms).

9 - Set RST to high (one).

10 - Do some delay (I did 1ms).

11 - Set TEST to low (zero).

After it, I did a 3 ms delay and sent a byte 0x80 via UART, but I got no response (byte 0x90 would expected).

Following the sequence describe above, I can reset the MSP, but just the user program starts, not the BSL program.

When I downloaded and uncompressed the slau319g.zip file, I saw another sequence in the "BSL_Files/BSL Scripter/source/BSL_IO_UART.c" file.

This another sequence is:

1 - Set RST and TEST to low (zero).

2 - Do a 250ms delay.

3 - Set RST and TEST to low (zero), again.

4 - Do a 10ms delay.

5 - Set TEST to high (one), making the first positive transition.

6 - Do a 10ms delay.

7 - Set TEST to low (one).

8 - Do a 10ms delay.

9 - Set TEST to high (one), making the second positive transition.

10 - Do a 10ms delay.

11 - Set TEST to low (one).

12 - Do a 10ms delay.

13 - Set RST to high (one).

14 - Do a 10ms delay.

15 - Do a 350ms delay.

16 - Clear/purge all serial data.

17 - Change the baud rate to 9601.

18 - Change the baud rate to 9600.

19 - Do a 350ms delay.

It's correct?

Inside Linux, I can't use 9601 baud rate because Linux has 15 constants for the 15 possible serial speeds, from 75 bauds to 115200 bauds. No other baud rate can be possible.

I really need you help for solve this problem.

Thanks in advance.

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DRV 8432 PWM_A, PWM_B, PWM_C AND PWM_D INPUT SIGNAL PATTERN FOR THE 2PHASE HYBRID BIPOLAR STEPPER MOTOR

January 13, 2014, 1:46 pm
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HELLO,

I AM TRYING TO CONNECT A 2 PHASE HYBRID BIPOLAR STEPPER MOTOR WITH DRV8432.  FOR NOW I AM USING PSoc3 TO GENERATE THE PWM INPUT SIGNALS. COULD YOU PLEASE LET ME KNOW WHAT SHOULD BE THE INPUT SIGNAL PATTERN FOR THE PWM_A, PWM_B, PWM_C AND PWM_D  TO RUN THE 2 PHASE HYBRID BIPOLAR STEPPER MOTOR IN FULL BRIDGE AND HALF BRIDGE.


ALSO WHAT SHOULD BE THE M3, M2 AND M1 PIN CONNECTIONS FOR TO RUN THE HYBRID BIPOLAR STEPPER MOTOR?

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text 3 digit 7 segment display

January 13, 2014, 9:48 am
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 1.I have got a problem , in a project i used 3 digit 7 segment common cathode display (HX04301BHB), 10 pins, i couldn't indicate pin, which pin is D0,D1,D2 and a b c d e f g
please help me!
Heart rate measurement from fingerti
Heart rate measurement from fingertip
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