Part Number: BQ20Z655-R1
The customer would like to know what is the maximum sink current on the SMB lines? The standard says they must sink 350 uA but can the hardware sink more? It is not shown in the datasheet.
Thank You,
George
Part Number: BQ20Z655-R1
The customer would like to know what is the maximum sink current on the SMB lines? The standard says they must sink 350 uA but can the hardware sink more? It is not shown in the datasheet.
Thank You,
George
Part Number: MSP430FR5730
Tool/software: Code Composer Studio
Dear colleagues,
we've developed our own board based on MSP430FR5730 MCU. We don't use an external oscillator and work with DCO.
When trying to configure DCO it doesn't work correctly. In fact we've been trying to simplify the clock init process and used examples from TI Resources explorer. None of them works as expected.
As a reference we used these code examples:
The issue is that actual clock frequency we've got is 8 times less. All dividers were set to 1, and still this doesn't help.
We're using CCS Version: 8.2.0.00007 to compile and build the project.
Could you please advise what might be wrong?
Part Number: BP-DAC11001EVM
Hi,
Is there any example source code for driving the DAC with the MSP-EXP432E401Y board? Or even the source available for the ACCTRL.bin file that is used to interface with the guicomposer program?
Part Number: TMS320F28069M
Tool/software: Code Composer Studio
Hi Guys,
i have question regarding my HVMotorCtrl+PfcKit_v2.1 with the TMS320F28069M Controll Card. I am trying to activate the CLA-Unit on the controller but I cannot flash the controller. I thing there is a problem with my Linker Command File.
I can compile the project without errors. But when I try to debug the controller a "Load programm Error" emerges. The console output is:
C28xx: Writing Flash @ Address 0x003f0ef8 of Length 0x00000173 (page 0)
C28xx: Erasing Flash Sector A
C28xx: Erasing Flash Sector B
C28xx: Erasing Flash Sector C
C28xx: Erasing Flash Sector D
C28xx: Erasing Flash Sector E
C28xx: Erasing Flash Sector F
C28xx: Erasing Flash Sector G
C28xx: Erasing Flash Sector H
C28xx: Writing Flash @ Address 0x003ec000 of Length 0x00003ff8 (page 0)
C28xx: Writing Flash @ Address 0x003efff8 of Length 0x00000f00 (page 0)
C28xx: Writing Flash @ Address 0x003f7ff6 of Length 0x00000002 (page 0)
C28xx: Writing Flash @ Address 0x003e4000 of Length 0x0000019a (page 0)
C28xx: Writing Flash @ Address 0x003f11a0 of Length 0x0000002e (page 0)
C28xx: Writing Flash @ Address 0x003f106b of Length 0x00000134 (page 0)
C28xx: Writing Flash @ Address 0x003e0000 of Length 0x00000450 (page 0)
C28xx: Writing Flash @ Address 0x003f0000 of Length 0x0000018c (page 1)
C28xx: Flash Programmer: Error encountered when writing to flash memory
C28xx: File Loader: Memory write failed: Unknown error
C28xx: GEL: File: ..\workspace_resolver_svn\Resolver_Lab\Flash\Resolver_Lab.out: Load failed.
The following file is my Command Linker File:
/cfs-file/__key/communityserver-discussions-components-files/171/F28069M_5F00_CLA_5F00_FLASH.txt
My memory map looks like this:
/cfs-file/__key/communityserver-discussions-components-files/171/Resolver_5F00_Lab.txt
If I am trying to flash the controller with Uniflash the verification prints the following error:
"[ERROR] C28xx: File Loader: Verification failed: Values at address 0x3F0000@Program do not match Please verify target memory and memory map."
Could you please help me to solve this problem? If you need additional information dont hesitate to ask.
With best regards
Manuel
Part Number: CC2640R2F
We are starting a new development with the CC2640R2F. We need to use the long range capability of the Ble5, so we are using the ble5stack simple_peripheral example. We want to split the app image and the stack image for future OAD posibility. In this User Guide page (http://software-dl.ti.com/simplelink/esd/simplelink_cc2640r2_sdk/2.20.00.49/exports/docs/ble5stack/ble_user_guide/html/cc2640/architecture.html#section-converting-lib-build-to-split-image) shows how to make it in IAR but we are using CSS so i tried thie guide:
e2e.ti.com/.../Converting-Library-Build-to-Split-Image-_2800_CCS_29002D00_1.pdf
The stack compiles no problem, but in the App part, when it compiles it show an error:
>> Compilation failure
Application/subdir_rules.mk:9: recipe for target 'Application/simple_peripheral.obj' failed
"../Application/simple_peripheral.c", line 2303: error #20: identifier "IDX_Gap_RegisterConnEventCb" is undefined
"../Application/simple_peripheral.c", line 2331: error #20: identifier "IDX_Gap_RegisterConnEventCb" is undefined
2 errors detected in the compilation of "../Application/simple_peripheral.c".
gmake: *** [Application/simple_peripheral.obj] Error 1
gmake: Target 'all' not remade because of errors.
It seems like some Stack linked funtions are mising. I don't know if i'm mising something, or if with CSS is not posible to split the images. Or if it will be posible to split in the near future.
CCS version: 9.2.0
SDK version: v3.30.00.20
Stack version: v2.2.3
Part Number: DAC38J84
Dear Helpers,
We are developing a system wherein DAC38J84 receives DACCLK from LMK04828 DCLKout2.
The DAC PLL is bypassed in DAC38J84, such that the DACCLK pins provide the SerDes PLL reference input directly.
Now that everything is working fine from power up, we would like to adjust the phase of DACCLK on the fly by applying LMK04828 dynamic digital delay to DCLKout2.
Unfortunately, delaying or advancing DCLKout2 by a single VCO cycle causes the DAC38J84 JESD RX FSM to assert SYNCb.
I suspect that the JESD link breaks for this reason: The SerDes PLL momentarily loses lock when the DACCLK interval is abruptly stretched or shortened for one cycle, therefore the JESD RX FSM resets, therefore the JESD link needs to be re-established.
Q1) would you kindly confirm my understanding of the phenomenon that we are observing?
Q2) I'm wondering whether we could harness the DAC PLL to allow on-the-fly DACCLK phase adjustment without breaking the JESD link?
Hopeful thanks --todd
Part Number: UCC21750
Hi,
I am aware that the UCC21750 can process both differential PWM pair and single-ended PWM, however, my questions are:
When the single-ended PWM is applied, does the IN- need to be connected to GND?
When the differential PWM pairs are applied, the maximum IN+ and IN- applied is also VCC (5V)?
Many thanks
Weichi
Part Number: DRV110
Hi TI team,
In our database we have a B version of the datasheet while the current version is G.
The C revision changed the minimum Rosc resistor to have a maximum frequency of 25kHz while it was 60kHz maximum, see below:
Initially we used this component with a 40kHz frequency. Why did you limit the consumer with a maximum frequency of 25kHz?
Thanks in advance!
Part Number: TDP158
Hi team,
As title, does TDP158 support HDMI 2.0b or HDMI 2.1?
In the datasheet,
in the feature section mentioned " Input to HDMI2.0a TMDS Physical Layer Output Supporting up to 6 Gbps Data Rate, Compatible with HDMI2.0a Electrical Parameters"
in the description section mentioned " Redriver supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b and 2.0b output signals."
These two graph are confusing me that is TDP158 able to support HDMI 2.0a and HDMI 2.0b but not HDMI 2.1 right?
Part Number: SN6501
Hi,
I have an application question regarding SN6501: if the transformer is shorted on the secondary side, will the part protect itself? I.e. is there either a current limit imposed by the part , or a thermal shut-down?
Thank you!
Regards,
Alberto
Part Number: TPS25810
Hello,
I have a design with a TPS25810RVC as a USB-C controller to implement a USB-B 3.0 to USB-Type-C solution.
I used a TPS25810 as a controller and the HD3SS3212 switch for USB data signals. A USB-C to USB-C cable connect my design to a UTP with a TPS65982 power delivery and a FX3.
I have an issue when, after a negotiation and normal use of the two design, I disconnect the USB-C cable on UFP side. This problem occur with USB-C to USB-C cable with length >1m. (This one for example: https://www.digikey.ch/product-detail/en/jae-electronics/DX07518S20K18747/670-2984-ND/7902281). The disconnection is not correctly detected.
By monitoring VBUS, CC1 and CC2 lines with an oscilloscope, it seems that after 150ms the device reactivate VBUS voltage. I guess it is because due to residual voltage on CC lines (around 350mV on CC1 after 150ms) is the cable is too long?
I would like to use a 2m USB-C to USB-C cable and for the UTP the power delivery (TPS65982) is configured as USB3 gen1 so it should be ok to use this type of cable.
I tried a design with and without the overvoltage protection, folowing figure 1 of SLVA751 document ( http://www.ti.com/lit/an/slva751/slva751.pdf )
or figure 15 of TPS25810 datasheet.
Do you have an idea of this re-activation? the issue is that if a reconnect the UTP device, the negotiation is failing.
Best regards,
Foucauld
Hello,
My small group had been exchanging w/several forum users & a vendor agent - and 'suddenly & unexpectedly' - all the 'history' of these exchanges has disappeared!
It is w/in forum's 'rights' to make such a change - yet 'basic' consideration for your users - suggests that (some) warning be provided!
As semiconductor Sales have dropped - 'Cutting the link between forum members 'in need' - and those pledged to 'assist' - appears counter-productive...
This 'draconian' measure occurred w/in the past hour - even impacts the ability of my group & a vendor agent - to assist a forum user to a highly complex 'solution.'
No feeb tags
Part Number: TMS320F2808
Hello,
after manufacturing test of boards some of the boards showed strange behaviour after the test sequences. In such cases, the two TMS320 devices became locked. The root cause is currently unknown.
In order to track the problem further, we implemented various CMSSCR read procedures into the test flow.
Before programming: 0050H
After programming: 0070H
This is true for all variants of this board and also for other boards using the same TMS320 device.
Now the question:
When reading the CSMSCR register of some other boards, we see CSMSCR values:
DSP1 = 0047H
DSP2 = 0041H
But they should be 0050H... What do these values mean? Is there a table describing the values further?
Many thanks in advance!
Part Number: SN6501
Hi,
I have an application question regarding SN6501: if the transformer is shorted on the secondary side, will the part protect itself? I.e. is there either a current limit imposed by the part , or a thermal shut-down?
Or would it be better to use SN6505B, which explicitly references the Ilim feature?
Thank you!
Regards,
Alberto
Part Number: AM5728
Hello,
We have a custom carrier board that uses an AM5278 processor that is connector to a FPGA via PCIe. On the carrier board is a clock generation chip to create a common clock which feeds the AM5278 and the FPGA for PCIe clocking.
Everything works exactly as expected if we turn off Spread Spectrum clocking, but inorder to meet some EMI levels we need to enable Spread Spectrum. When we do enable it the AM5278 fails to link to the FPGA.
Does the AM5278 support spread spectrum clocking with the PLL that runs the PCIe portion? If so are there settings required to make it function.
Thank You,
Brian
Part Number: LAUNCHXL-CC26X2R1
Tool/software: Code Composer Studio
Dear,
I understand .cfg files are kernel configuration files.
However, I do not understand the relationship they have with .xscfg files.
First I guessed my .cfg file would become the same as the selected build configuration (.xscfg) file every time I build but it does not seem to be the case.
Please, let me know.
Part Number: ISO1050
Hi Sir,
May I learn from you about ISO1050 datasheet P.22 9.2 Typical Application SCH, why the GND2 need a cap to the PE?
Is this the Y-cap to immunity CM noise?
If so, how to determine this Y-cap value?
Thank you.
Edward Chen
Part Number: TMS320F2812
I had some questions about the stack on the TMS320F2812 since I'm currently running into issues with stack running out of space.
The board I'm working with has an external memory of size 256KB connected to XINTF zone 2. Currently, all data memory in the program is being placed at the start of external memory, and stack has full use of the L0 and L1 SARAM starting at address 0x8000. The problem is that L0 and L1 only total 8KB, and the stack is growing larger than that.
Are there any larger memory regions on the TMS320F2812 that are available for use as the stack? I wanted to use the external memory, but it looks like the stack pointer is only 16 bits, so it can't point at that address. I was having trouble finding the right document for thechip though, so I could be wrong about that. Can you confirm my understanding of that as well?
Thank you for your time and any help!
Part Number: DLP-7970ABP
Tool/software: TI C/C++ Compiler
Hi,
I am facing issue while trying to build these sample code. I am using the Code Composer Studio Version: 9.2.0.00013.
While building it is showing make not found in path error. The project properties is showing some compiler mismatch error as shown in the attached image.
I tried uninstall and install the mentioned compiler, but seems it is not installed properly. Hope there is some issue. I tried to install using install new software option under help menu.
Please let me know ASAP.
Thanks and Regards,
Sunil
Part Number: UNIFLASH
Tool/software: Code Composer Studio
We are upgrading from version 3.4 to 5.1 on a station that has multiple XDS200 devices hooked up trying to program multiple TMS320F28377D devices. We have used 5.1 on single-up stations w/o issue.
Using the UniFlash GUI I can program one of the 4 boards (the one that corresponds to index 0) but not the other 3. And I can use dslite (like explained below) when all 4 are hooked up but only index "0" works.
Some details:
I have replicated this on both Windows 7 and 10. Thanks.