Part Number: TPS51225C
Hi
1. What is the maximum power that TPS51225C can provide using charge pump?
Depends on external charge pump circuit?
2. Could it be possible to generate 12V output?
BestRegards
↧
TPS51225C: Ability of power supply using Charge pump
↧
OMAP-L138: NAND ECC Issue
Part Number: OMAP-L138
Hi All,
We are trying to interface Winbond W29N04GV 512 MB NAND flash with Omapl138 LCDK, In u-boot I am trying write a pattern from ram location to NAND flash that write is getting fail, I added some prints and found that that data will write into the flash correctly but while verifying that data the ECC calculation and correction is happening in correction stage the we are setting the corresponding bits in NANDFCR to calculate the ECC and checking the NANDFSR register for the errors it is returning 0x01 in ECC_STATE bit field.
We are using 4-bit ECC in both kernel and u-boot, In kernel we are trying to flash a UBI filesystem, after flashing we cannot able to attach the ubifs we are getting some error like bit flipped in PEB 0. We cannot rectify what the issue is please can anyone share me the configurations or any driver patchs for kernel and u-boot to solve this issue.
Thank You
Deepak H M
↧
↧
LSF0102: Logic forum
Part Number: LSF0102
Dear Sir/Ms.
When using R2 to design the voltage of Vref_A, is it as follows:
Vref_A=1.5V@VPU=3.3VDevice 1.5-5.5V
Vref_A=1.0V@VPU=3.3V Device 1.0-5.5V
There is also VTH related to the calculation of the value of R2. What is the parameter of VTH?
Best Regards,
Kami Huang
↧
DS90UB954-Q1EVM: I2C Communication stops when J16 VDDIO set to VDD3V3 3.3V
Part Number: DS90UB954-Q1EVM
Hello,
I have a DS90UB954-Q1EVM board communicating with a 953 serializer in a camera, connected through a Fakra connector to J29. The device is locked.
The DS90UB954-Q1EVM board appears to stop communicating with ALPS when the J16 VDDIO voltage select jumper is set to VDD3V3 3.3V.
The user guide indicates Pin 1-2 are shorted together to use 3.3V as the default, but my device was received with pins 2-3 connected, to use 1.8V.
At 1.8V, ALPS correctly identifies the connected serializer as a 953 and locked. If the jumper is moved, the app hangs until the 1.8vio is restored.
If the app is started with the jumper set to 3.3V, it identifies the serializer as 913, and not locked, despite the lock LED D9 glowing.
I would like to use J25 to connect to I2c using 3.3V instead of 1.8V. Other EVMs work at 3.3V i2c.
J25 is not currently connected to any external device.
I have consulted hsdc007_reva_evm.pdf for the updated schematic with the wiring of I2C connector J25 (opposite of Table 6) and J16.
Thank you,
J
↧
UCC28063A: UCC28063A PFC DC level Accuracy
Part Number: UCC28063A
For same circuit making two set power stage and get different PFC output DC Level, one is DC395V and another is DC406V,How can this situation be improved ?
B/R James
↧
↧
DRV2510-Q1: Noise on output signal and relation to reserved bits in register 0x03
Part Number: DRV2510-Q1
We're currently developing firmware for the TI DRV2510-Q1 driver in one of our medical imaging applications. We’re driving a couple square waves into the IN+/IN- pins of the driver. We’re seeing a lot of noise on the OUT+(yellow trace)/OUT-(blue trace) pins which could cause issues in our image quality:
Zooming in, we found the noise to be 400kHz, the driver PWM frequency:
If I write 1 to register 0x03 bit0 I could change the frequency of the noise to 500kHz, confirming the noise source.
Here’s where things get interesting, I accidentally discovered that if I write 1 to bit 2(a reserved bit) of register 0x03, the noise goes away:
Although the datasheet didn’t specify a default value, I could read the default value on power up to be 0x78 for register 0x03. Bit 2 is zero by default.
In fact, I found that both reserved bits bit 1 and bit 2 has some effect on noise, writing a 1 to bit 2 appears to remove it. While doing this yields the desired behavior, I’m not comfortable driving a reserved bit. Please let me know if this is safe.
FYI, in these tests the driver is not connected to any load, standby pin is set to 0, en pin set to 1, register dump:
register 0x00 : 0x04
register 0x01 : 0x04,
register 0x02 : 0x84
register 0x03: 0xBE ( no noise with this value)
Thanks,
Tian
↧
TPA3255EVM: TPA3255EVM full load test Issue
Part Number: TPA3255EVM
Do we have TPA3255EVM full load test report ?
My Customer offer DC48V and setting PBTL Mode for 2ohm load ,
only get max 300W power output can't get 600W.
In same condition TPA3251 (DC36V) can get 300W power output.
B/R James
↧
TDP142: Mismatched Order of Pin Define
Part Number: TDP142
Dear Team,
My customer is using TDP142 for Notebook eDP application.
But they didn't aware that TDP142's pin define doesn't match the connector. Therefore, they need to modify the layout to fix it.
They want to know what is the reason TDP142 has mismatched pin define for the connector.
Could you please help to explain for us? Thank you.
↧
CCS/CC1310: CC1310 I2C Problem
Part Number: CC1310
Tool/software: Code Composer Studio
I can't use the I2C driver without calling
Display_open function. Why can't we use the I2c without calling Display_open which opens a Uart. The below code works if i call Display_open but commenting Display_open cause the I2C to stop working.void*mainThread(void*arg0) { uint8_t txBuffer[1]; uint8_t rxBuffer[2]; I2C_Handle i2c; I2C_Params i2cParams; I2C_Transaction i2cTransaction; /* Call driver init functions */ I2C_init(); /* Open the HOST display for output */ display = Display_open(Display_Type_UART, NULL); if(display == NULL) { while(1); } /* Create I2C for usage */ I2C_Params_init(&i2cParams); i2cParams.bitRate = I2C_400kHz; i2c = I2C_open(Board_I2C_TMP, &i2cParams); if(i2c == NULL) { //Error Initializing I2C while(1); } else{ //I2C Initialized! } txBuffer[0] = data; //Tx data i2cTransaction.slaveAddress = DEV_ADDR; //device address i2cTransaction.writeBuf = txBuffer; i2cTransaction.writeCount = 1; //number of bytes to send i2cTransaction.readBuf = rxBuffer; //memory location to save read data i2cTransaction.readCount = 2; //num of bytes to save if(I2C_transfer(i2c, &i2cTransaction)) { // Transaction was a success, handle the data } else{ // Transaction failed } /* Deinitialized I2C */ I2C_close(i2c); return(NULL); }↧
↧
TUSB2046B: SI test inquire
Part Number: TUSB2046B
Hi Sirs,
Sorry to bother you.
Currently testing USB HUB has encountered some problems,
We want to connect the TUSB2046BVFRG4 HUB on the PMB via USB via Xhci on the PC, and then use the xhci tool to make the hub output the package to the downstream (upstream is PC), but it has not been successful.
We would like to know how to test the USB 2.0 signal (currently, the downstream has 4 DEVICEs).
Step1
Step 2
We have tried to remove the Rpu 1.5k but it still can’t send out the test pattern..
Schematic:
↧
TPS65941 Tape and Reel information
For the TDA4X PMIC, looking for information on the tape/reel:
the complete, orderable part number
MSL
Max reflow temperature
Lead finish
Tape width
Component pitch
Component orientation
Any help appreciated!
↧
CCS/MSP430F5529: UART receive is interrupted by timer interrupts
Part Number: MSP430F5529
Tool/software: Code Composer Studio
Hello,
I'm using USCI_A0 to send/receive through UART and timer A0. However, I'm missing some bytes when I receive UART when I have timer interrupts enabled. If they aren't enabled, I have no issues. I thought that UART interrupts are higher priority interrupts which means that this shouldn't really be the case. I'm not sure how to fix this?
↧
TDA2SA: About DDR Memory change Issue
Part Number: TDA2SA
Hi SIr
We used TDA2 for development and we change the DDR P/N and size (512MB).
Where should we modify about DDR timing setting and memory size setting ?
As we know , we should modify SBL first.
Do we need to modify other parts to let system can boot successfully and work well. ( for example : where to modify size for app image)
please advise
BR
Yimin
↧
↧
TPS54140: Parallel Configuration
Part Number: TPS54140
Hi,
Good day!
Our customer wants to know if the TPS54140 can be configured in parallel operation for higher output current.
They are making a PCB for this. Currently their requirement is a converter for 5V @ 1.5A however they want to make space for a parallel converter to increase the output current in the future if needed.
Looking forward to your response.
Thank you and have a great day.
Regards,
Cedrick
↧
ADS1278EVM-PDK: semi-Standalone mode, using Motherboard power supply: J4 isolation?
Part Number: ADS1278EVM-PDK
I have the ADS1278EVM on top of the modular motherboard (MMB0, Rev D).
I need to interface the EVM to an FPGA via J4 for control and J2 for the 8 serial data channels, using it in SPI mode, low-power mode, with 4.096 MHz input clock, 16.0 KSPS serial output (digital audio).
I would like to keep the EVM connected to the MMB0 thru all three headers (J3, J4, J5) for mechanical stability and to take advantage of the MMB0 power supply (J5), but otherwise use the EVM in standalone mode.
It looks like the analog input EVM/J3 pins (which go to MMB0/J10) are sufficiently isolated; i.e., not driven or loaded by the motherboard.
But I can't tell if the control pins on EVM J4 are sufficiently isolated (not driven by MMB0 J4) to directly connect my FPGA to EVM J4.
I have a Rev C. MMB0 schematic (could not find Rev D), which shows much of J4 being isolated by the FET switch U4 when U4/DCEN = 1, which I'm guessing is the default value unless an I2C write from the MMB0 processor changes it.
But I don't know if I can guarantee the processor won't eventually enable MMB0/U4, or if other pins on MMB0/J4 that aren't connected to MMB0/U4 are sufficiently isolated.
Note: I don't plan to use the ADC-Pro software in this configuration, or have the MMB0 processor do anything other than its normal background/idle stuff.
On EVM/J4, I need to drive
MODE[1:0] = "10" (pins 6,2), (but will omit these if it is safe to set non-default values on DIP switch S2).
FORMAT[2:0] = "010" (pins 14,12,8), (but will omit these if it is safe to set non-default values on DIP switch S2).
SYNCn = "1" (pin 1),
CLKSEL = "0" (pin 19),
CLK = 4.096 MHz (pin 17),
and receive
SCLK = 512 KHz (pin 3),
DRDYn = 16.0 KHz (pin 15).
I don't (think I) care about CLKR (pin 5), FSX (pin 7), FSR (pin 9), Dx (pin 11), DR (pin 13), SCL (pin 16), or SDA (pin 20) since I'm using SPI mode and not outputting the modulator clock.
THE QUESTIONS:
1. For the above scenario, do I need to completely isolate EVM/J4 from MMB0/J4 (e.g., clip the pins off MMB0/J4 so they don't conflict with my FPGA drive & receive)?
1a. If so, do we lose the pull-up resistors from MMB0 that keep the SCL & SDA pins from floating (as inputs to EVM U7, U8, and U14), and if so, would this be a problem?
2. Can I safely use the DIP switches on S2 for FORMAT[2:0] and MODE[1:0] instead of driving them with my FPGA?
3. Can I safely set the DIP switches on S1 to POWER-UP all 8 ADC channels? If the I2C port expanders are only reading these pins (never trying to write them), there should be no conflict.
4. The EVM-PDK User's Guide (SBAU197A–February 2012–Revised January 2016) in Section 5.6 (Power Supply Header, J5) states,
The ADS1278 digital supplies are connected as follows:
• IOVDD supply is connected to the +1.8VD pin of the J3 header.
• DVDD supply is connected to the +3.3VD pin of the J3 header.
Are the two bullets above backward? Everything on the EVM and MB schematics suggest a 1.8v core voltage (DVDD) and 3.3v I/O voltage (IOVDD); in particular, MMB0 (Rev. C) schematic shows
J5/7 = +1.8VD (EVM J5/7 = DVDD)
J5/9 = +3.3VD (EVM J5/9 = IOVDD)
Thanks very much!
MarkJ
↧
DLP4710: Software controlling frame rate in Linux
Part Number: DLP4710
Hi! We have a couple of 4710s that were programed to run at 120Hz in Windows PCs. We'd now like to be able to do the same (i.e., run it at 120Hz) in Linux. Is there an equivalent app?
Thanks!
cher
↧
Search TI condition(see contenct)
Hi,
Search TI condition as below:
Have any TI solution can match?
1.DP hub IC, VMM5330, Synaptics
2.Have any refer circuit
Warm Regards,
Lin
↧
↧
TRPGR30ATGC: Range
Part Number: TRPGR30ATGC
Hello,
We are using TRPGR30ATGC for animals tagging.
We would like to have about 20 to 30 cm of reading range in front of the reading antenna. Is this possible?
Currently we're struggling to get more than 7 cm of range with the reader we've designed. Antenna (160µH) dimensions are around 10cmx10cm with around 1000V pk to pk antenna voltage.
The demodulation circuit is based on simples HV diodes with analog filters and a comparator. Should we be able to get a better range with this architecture?
Do we have to use direct sampling and digital demodulation to increase the range?
Thanks in advance,
Victor
↧
TMP461: transistor selection requirement?
Part Number: TMP461
Hi Sir,
Do we have any limitation of selecting transistor for TMP461?
Or just choose a general transistor of 2N3904(NPN) or 2N3906 (PNP) are fine.
My question is:
If general transistor of 2N3904(NPN) or 2N3906 (PNP) are fine, why we list the 4 criteria in as below?
Could you please help to verify attached transistor are all fine for TMP461?
Thanks
(Please visit the site to view this file)
(Please visit the site to view this file)
↧
ADS1675: tradeoff to reduce power consumption? Rbias resistor at for 25Mhz?
Part Number: ADS1675
Team,
The ADS1675 would be interesting for a project but the nominal power consumption is too high.
-Are there ways to reduce the power consumption significantly? What would be the tradeoff?
In the same condition the consumption is much higher than the ADS127L01.
-For a clock speed of 25Mhz:
What Rbias resistor values can be used? is 30k OK? What would be the impacts on the performances?
Datasheet only answers for 8, 16 and 32Mhz.
-What is the input impedance of the ADC? Do we have information to dimension the anti-aliasing filter?
Thanks in advance!
A.
↧