Part Number:MSP432P401R
Tool/software: TI C/C++ Compiler
Hello.
I've run into a problem where I'm trying to add two large numbers and I'm losing the carry bit when I increase the optimizer level to 2.
To demonstrate the problem I have lightly modified the uart loopback example (uart_loopback_24mhz_brclk.c). At none, 0 or 1 optimization it outputs a "y" for successful result.
At level 2 and above, I get a "n". The carry bit is not being carried between each 32bit addition.
Is this user error, or failure of the optimizer? I've tried a for() loop instead of while() and get the same result.
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/******************************************************************************
* MSP432 UART - Loopback with 24MHz DCO BRCLK
*
* Description: This demo connects TX to RX of the MSP432 UART
* The example code shows proper initialization of registers
* and interrupts to receive and transmit data. If data is incorrect P1.0 LED
* is turned ON.
*
* MCLK = HSMCLK = SMCLK = DCO of 24MHz
*
* MSP432P401
* -----------------
* | |
* RST -| P1.3/UCA0TXD|----|
* | | |
* -| | |
* | P1.2/UCA0RXD|----|
* | |
* | P1.0|---> LED
* | |
*
*******************************************************************************/
/* DriverLib Includes */
#include <ti/devices/msp432p4xx/driverlib/driverlib.h>
/* Standard Includes */
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
uint8_t TXData = 1;
uint8_t RXData = 0;
/* UART Configuration Parameter. These are the configuration parameters to
* make the eUSCI A UART module to operate with a 115200 baud rate. These
* values were calculated using the online calculator that TI provides
* at:
* software-dl.ti.com/.../index.html
*/
const eUSCI_UART_Config uartConfig =
{
EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
13, // BRDIV = 13
0, // UCxBRF = 0
37, // UCxBRS = 37
EUSCI_A_UART_NO_PARITY, // No Parity
EUSCI_A_UART_MSB_FIRST, // MSB First
EUSCI_A_UART_ONE_STOP_BIT, // One stop bit
EUSCI_A_UART_MODE, // UART mode
EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling
};
uint32_t BigAdd(uint32_t *result, const uint32_t *x,
const uint32_t *y, size_t size)
{
uint64_t carry = 0;
while (size > 0) {
carry += *x++;
carry += *y++;
*result++ = (uint32_t)carry;
carry >>= 32;
--size;
}
return (uint32_t)carry;
}
const uint32_t one_256bit[8] = {0x00000001, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000 };
const uint32_t efs_256bit[8] = {0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF };
int main(void)
{
uint32_t result[8];
/* Halting WDT */
MAP_WDT_A_holdTimer();
/* Selecting P1.2 and P1.3 in UART mode and P1.0 as output (LED) */
MAP_GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P1,
GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION);
MAP_GPIO_setAsOutputPin(GPIO_PORT_P1, GPIO_PIN0);
MAP_GPIO_setOutputLowOnPin(GPIO_PORT_P1, GPIO_PIN0);
/* Setting DCO to 24MHz (upping Vcore) */
FlashCtl_setWaitState(FLASH_BANK0, 1);
FlashCtl_setWaitState(FLASH_BANK1, 1);
MAP_PCM_setCoreVoltageLevel(PCM_VCORE1);
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_24);
/* Configuring UART Module */
MAP_UART_initModule(EUSCI_A0_BASE, &uartConfig);
/* Enable UART module */
MAP_UART_enableModule(EUSCI_A0_BASE);
/* Enabling interrupts */
MAP_UART_enableInterrupt(EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT);
MAP_Interrupt_enableInterrupt(INT_EUSCIA0);
MAP_Interrupt_enableSleepOnIsrExit();
if(BigAdd(result,one_256bit,efs_256bit,8))
MAP_UART_transmitData(EUSCI_A0_BASE, 'y');
else
MAP_UART_transmitData(EUSCI_A0_BASE, 'n');
while(1)
{
MAP_UART_transmitData(EUSCI_A0_BASE, TXData);
MAP_Interrupt_enableSleepOnIsrExit();
MAP_PCM_gotoLPM0InterruptSafe();
}
}
/* EUSCI A0 UART ISR - Echos data back to PC host */
void EUSCIA0_IRQHandler(void)
{
uint32_t status = MAP_UART_getEnabledInterruptStatus(EUSCI_A0_BASE);
MAP_UART_clearInterruptFlag(EUSCI_A0_BASE, status);
if(status & EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG)
{
RXData = MAP_UART_receiveData(EUSCI_A0_BASE);
if(RXData != TXData) // Check value
{
MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P1, GPIO_PIN0);
while(1); // Trap CPU
}
TXData++;
MAP_Interrupt_disableSleepOnIsrExit();
}
}
