Part Number:DAC8771
Hello E2E,
Please let me know about settings.
About address 0x06;
When want to Back-Boost operate, DCA-bit is "1". <- Is it OK?
Is DCA-bit the ENABLE of Buck-Boost converter?
About address 0x07;
What is "arm" of Buck-Boost converter?
LP and LN ports? Or internal power switch?
Regards,
ACGUY
Part Number:CC3200-LAUNCHXL
Tool/software: Code Composer Studio
Hello,
Can anyone please help me in setting two CC3200 in transceiver mode, means what is the steps to setup this?
i need to communicate between the two CC3200 devices like exchanging small texts using the devices .
CC3200 (unit a) <-------> cc3200 (unit b) i need to communicated small texts from these devices.
Part Number:TPS61088
Hi TI Team,
I am currently working on wireless charging. I am planning on adding a regulator to stabilize the output voltage. After some testing, I find out that the output voltage would be as high as 20 V if there is no load. If load is connected, voltage input times the current drawn is approximately a constant. I found that TPS61088 is pretty much fit my need but the input voltage limit is 12V. Is it fine for me to use it in my application? The voltage input at startup would exceed the limit for a short time. The regulator will connect to the load all the time. The only concern would be the inrush voltage will kill the regulator or not. My current plan is to add a filter to limit the inrush power. Is it fine to deal with the problem? Thanks for any replies.
Regards,
Zeon
Part Number:OPA2316
Hi Sirs,
Sorry to bother you.
Refer to the datasheet.
The red mark below does not match the 0.58mm.
Could you please confirm & modify the SPEC, change the red mark to 0.575mm and re-update the specification.
[(1.85-0.7)/2]=0.575mm
Part Number:LAUNCHXL-F28027
Tool/software: TI C/C++ Compiler
Hi guys,
I am using LAUNCHXL-F28027, which comes with the TMS320F28027PT controller and i am using generic type linker command file attached below :
/* //########################################################################### // // FILE: F2802x_generic_flash.cmd // // TITLE: Generic Linker Command File for f2802x devices // //########################################################################### // $TI Release: F2802x Support Library v3.02.00.00 $ // $Release Date: Thu Oct 18 15:45:37 CDT 2018 $ // $Copyright: // Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### */ /* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in <base>\headers\cmd // // For BIOS applications add: F2802x_Headers_BIOS.cmd // For nonBIOS applications add: F2802x_Headers_nonBIOS.cmd ========================================================= */ /* ====================================================== // For Code Composer Studio prior to V2.2 // -------------------------------------- // 1) Use one of the following -l statements to include the // header linker command file in the project. The header linker // file is required to link the peripheral structures to the proper // locations within the memory map */ /* Uncomment this line to include file only for non-BIOS applications */ /* -l F2802x_Headers_nonBIOS.cmd */ /* Uncomment this line to include file only for BIOS applications */ /* -l F2802x_Headers_BIOS.cmd */ /* 2) In your project add the path to <base>\headers\cmd to the library search path under project->build options, linker tab, library search path (-i). /*========================================================= */ /* Define the memory block start/length for the F2802x PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F2802x are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. Contiguous SARAM memory blocks or flash sectors can be be combined if required to create a larger memory block. */ MEMORY { PAGE 0: /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ FLASHA : origin = 0x3F7000, length = 0x000F80 /* on-chip FLASH */ CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ FLASHB : origin = 0x3F4000, length = 0x003000 /* on-chip FLASH */ // changed by hima FLASHC : origin = 0x3F2000, length = 0x002000 FLASHD : origin = 0x3F0000, length = 0x002000 IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */ IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */ IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */ ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ RAMM1 : origin = 0x000100, length = 0x000700 /* on-chip RAM block M1 */ RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 *///changed line by hima //RAML1 : origin = 0x3F8000, length = 0x001000 // hima written } /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM */ SECTIONS { /* Allocate program areas: */ codestart : > BEGIN PAGE = 0 ramfuncs : LOAD = FLASHA, RUN = RAMM0, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), RUN_START(_RamfuncsRunStart), PAGE = 0 .cinit : > FLASHA | FLASHB, PAGE = 0 .pinit : > FLASHA | FLASHB, PAGE = 0 .text : >> FLASHA | FLASHB | FLASHC |FLASHD, PAGE = 0 csmpasswds : > CSM_PWL_P0, PAGE = 0 csm_rsvd : > CSM_RSVD, PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > RAMM1, PAGE = 1 .ebss : >> RAMM1 | RAML0, PAGE = 1 .esysmem : >> RAMM1 | RAML0, PAGE = 1 //.ebss : > RAMM0, /* Initalized sections go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : >> FLASHA | FLASHB, PAGE = 0 .switch : >> FLASHA | FLASHB, PAGE = 0 /* Allocate IQ math areas: */ IQmath : >> FLASHA | FLASHB, PAGE = 0 /* Math Code */ IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD /* Uncomment the section below if calling the IQNexp() or IQexp() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD { IQmath.lib<IQNexpTable.obj> (IQmathTablesRam) } */ /* Uncomment the section below if calling the IQNasin() or IQasin() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD { IQmath.lib<IQNasinTable.obj> (IQmathTablesRam) } */ /* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ /* DSECT */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS PAGE = 0, TYPE = DSECT } /* //=========================================================================== // End of file. //=========================================================================== */
Here, i am using to RAM blocks i.e. RAMM1(origin = 0x000100, length = 0x000700) & RAML0 :(origin = 0x008000, length = 0x001000 ).
See the memory allocation details below:
I am getting this type of error :
"../F2802x_generic_flash.cmd", line 160: error #10099-D: program will not fit into available memory. run placement with alignment/blocking fails for section ".ebss" size 0x1c17 page 1. Available memory ranges:
RAMM1 size: 0x700 unused: 0x0 max hole: 0x0
RAML0 size: 0x1000 unused: 0x0 max hole: 0x0
error #10010: errors encountered during linking; "Power_Bank_Display.out" not built
I have one more RAM block left with which can found from the memory mapping of the F28027 controller, but when i try to access that particular block i am unable to get the expected results, with the fine code as well.
Can any one tell me the alternative?
Thanks & regards
Himavanth
Part Number:TDC1000
Hello support, i'm going to develop one produce based TDC1000 . in which i'm using HT-300PLT/R10081(300 khz) .i have attached datasheet for same sensors.TDC1000 generating pulses but sensors are not responding at receiving.so i need support from your side .so i can use your ics easily for mass production. if any one client or you have experience on same sensors.please help me(Please visit the site to view this file)
Part Number:AM3358
Tool/software: Linux
Hi,
CPU : AM335X-GP rev 2.1
The customer wanted to build custom diver into kernel. Below is error log:
[ 11.927340] can_dev: disagrees about version of symbol module_layout
[ 12.278743] can_dev: disagrees about version of symbol module_layout
[ 10.450504] musb_am335x: disagrees about version of symbol module_layout
Driver info:
modinfo can-dev.ko
filename: /home/root/can-dev.ko
license: GPL v2
description: CAN device driver interface
srcversion: 0A0DFC2826FEF000B5C4F56
depends:
intree: Y
name: can_dev
vermagic: 4.14.79-rt47-g28d73230da preempt mod_unload modversions ARMv7 p2v8
Part Number:CC3200
Tool/software: TI-RTOS
Hi,
I am trying to connect IBM cloudant nosql database with secure connection with DigiCert SHA2 Secure Server CA with signed sha256 certificate,I generated a .der version of that CA certificate, i am getting SL_ESEC_ASN_SIG_CONFIRM_E and SL_ESEC_HANDSHAKE_FAILURE error with sl_connect.
Thanks,
Nagaraj
Part Number:BQ76PL455A
bq76PL455A can supports max 16cells, and it can stack up to 16 devices.
So I think maximum supported cell number is 256. (16 cells x 16 devices)
If we want to monitor over 256 cells, is it possible to use bq76PL455A?
For example, can we use bq76PL455A as attached system block(similar with App note SLUA785 Fig 19) when we want support 386 cells?
Please let me know If you have recommended constitution and external peripheral devices.
(Please visit the site to view this file)
Best Regards,
Kohei Sasaki
Part Number:DLPC910
Dear All,
Our DLPC910 board is initialized.
We're trying to communicate with the DLPC910 board via I2C (using another FPGA board), however, we cannot get the Acknowledge from the DLPC910.
We've followed the DLPC910 datasheet "Example I2C Master Reading DLPC910 Register Data", and since that our DDC_IIC_ADDR_SEL is pulled up internally, we write and read to the address 0x36.
And Here is our I2C signal:
Thank you for your time.
Sincerely,
Justin
Part Number:TDA2PXEVM
Tool/software: Linux
Hi,
Image capture and memory dump are ok in DCC, and DCC file which is included in program image is also ok.
Sensor id in DCC was set up correctly. But "Update Current DCC" is not working.
Please find the following err log.
<DCC side>
Request to Update active DCC data in Target : 10.159.171.31
Loaded communication DLL:itCommun.dll
Error in Updating current DCC bin data
<TDA2Px EVB side>
[HOST] [HOST ] 1262.919203 s: NETWORK_CTRL: Received command [iss_send_dcc_file], with 173 bytes of parameters
[HOST] [HOST ] 1262.919538 s: NETWORK_CTRL: Network_read() failed to read parameters (port=5000) !!!
[HOST] [HOST ] 1262.919538 s: NETWORK_CTRL: iss_send_dcc_file:
[HOST] [HOST ] 1262.919843 s: NETWORK_CTRL: Sent response for command [iss_send_dcc_file], with 0 bytes of parameters
Regards,
HJ Kim
Part Number:AM3356
Tool/software: Code Composer Studio
Hi Experts,
We are looking for any on-board flash programming tool for mass production. The target memory is NOR or NAND flash. Does TI support this kind of tools?
Regards,
Uchikoshi
Part Number:BQ40Z50-R1
Hi, We have several batteries which fuse were blew out but we don't see any PF flag.
We have confirmed that the secondary protection IC didn't trigger the Fuse.
Our delta threshold of VIMR is 500mV and VIMA is 600mV.
Thank you for your help in advance.
Part Number:UCD3138
Tool/software: Code Composer Studio
Hi，
Test UCD3138PFC64EVM-026 with original code in UCD3138CC64EVM-030,it can be shown on the bottom of Device GUI Firmware Download page,as below:
(I've exported the original code from UCD3138CC64EVM-030 as " single phase.xo ",also I scan device in ROM mode first,and it can be found as " Found ROM v2 IC v3 ")
I downloaded PFC Firmware from http://www.ti.com.cn/tool/cn/ucd3138fw-pfc and followed SLUA677 trying to change the firmware into Interleaved mode:
And when I download the altered firmware , it tends to stay in ROM mode:
What I have modified is just the content shown in Pic.3 of system_defines.h. I've successfully download Interleaved firmware once before. So do I change the firmware incorrectly or any other actions of incorrectly operations? Please give me some advice.
Thank you. Your prompt reply will be highly appreciated.
Part Number:CC1310
Hi
Do you have a project example which has both WOR Rx and Tx? Prefer on TI-RTOS for CC13XX and CC26XX 2.21.01.01
Part Number:LM25141
Hi team,
May I know does LM25141-Q1 implement output OVP and UVP function?
It seems I can't find them on datasheet, but I found the PG pin UV/OV trip level in datasheet page #7 (EC table).
PG(UV) = 92% (typical)
PG(OVP) = 110% (typical)
Thank you.
Regards,
Allen
Part Number:TMS570LC4357
Hello,
I implemented a self test for the HF_LPO using the DCC (Dual Clock Compare) unit. So I selected my Reference clock to be the "OSCIN" and used the Values (Seeds, Valid0) generated by HALCoGen. The problem is, while running this test on several MCUs the Tolerance Window (Valid0Seed) varies too large. For one of the MCUs it is about 5.1% and for the other it is about 8.6% and so on.
Could someone please help me solving this issue, why the same test (DCC) on different MCUs from the same product family needs different Tolerance Windows?
Best Regards
Part Number:ADS8332
Hi,
How should we connect analog ground and digital ground?
1. directly together.
2. through a 0ohm resistor together
3. through small inductor together.
Does this method apply to all ADCs?
Part Number:TLV320AIC3104
Dear Supporters.
We use HP outs of TLV320AIC3104 to drive headphones,but the HP outs creat a 'pop' noise when powering up DAC.
Could you kindly help to give me some suggestions for this issue?If it is normal for TLV320AIC3xxx products？How to solve？
Thanks and Regards.
Joy Lu
Part Number:AM5746
Tool/software: TI-RTOS
Hi,
My customers was looking at the AM574x Errata i870.
They actually checked various accesses to PCIe Outbound / Inbound.
They were able to read and write byte data and halfwords with 32-bit unaligned accesses.
Question:
What kind of time (condition, processing) does incorrect mapping occur?
Regards,
Rei