TM4C1294KCPDT: Is there some timing difference here?

Part Number:TM4C1294KCPDT

Hi there,

I ran into a "strange" problem with my TM4C1294 project. I tracked it for a long time, and still have no found any obvious bug in my codes, so I am seeking help here:

I am using TM4C1294 to acquire data, paced by TiVa's internal periodical timer running off the 120Mhz system clock in both cases below

If I use external ADC (for higher end products), and acquire the data when the timer ISR is called (the max sample rate is below 200K), although there are some understandable jitter in time due to ISR/priority, everything seems working fine, and the sample frequency is what I expect, for example, 20.00Khz (measured by a frequency counter)

If I use TiVa's internal ADC for the lower end product, I let the same timer to trigger ADC sequencer, and acquire the data when ADC ISR is called, now the jitter is gone, but the sampling frequency seems to be off by a fraction, like 19.99Khz

The difference is higher than the tolerance (50ppm) of the master clock.

I wonder if there is a timing difference between the approach of Timer->ADC sequencer->ADC ISR and the approach of Timer->TimerISR->ADC, or maybe I have a hidden bug somewhere in my codes

Thanks!