Part Number:DAC38J84
I am having a troublesome problem on my design. I have a DAC38j84 being driven by an LMK04828 as is done exactly on the DAC38J84 eval board. I'm using the crystek 122.88 MHz oscillator as my reference. What I am seeing is an increase in SSB phase noise on my DAC clock (as seen by looking at a spare LMK output) when my JESD lanes are running. I've compared my layout to the eval board and don't see anything obvious other than I don't have the what looks like an attenuator on the sysref line. See attached image. 
There is no documentation on this circuit and I'm wondering if it is somehow providing some isolation between the DAC and LMK? Is there anything else anyone can think of as to how my JESD lanes are impacting the phase noise on the LMK DCLK outputs? You can see what I'm talking about below. The bright yellow trace is the DCLK6 output at ~2457.6 MHz. The darker yellow trace is the SSB phase noise with the JESD lanes on and scrambler activated. If I turn off the scrambler, I see discrete sidebands.
My setup is using 4x interpolation with a DDC NCO set at 450 MHz. DAC rate is 2457.6MHz with complex IQ signals.
