RTOS/TMS320C6678: FPGA writing steps to DSP by SRIO

Part Number:TMS320C6678

Tool/software:TI-RTOS

Hi

I set " C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_TputBenchmarkingTestProject " as my base project for communicating to FPGA by SRIO.

I accomplished this steps:

1) set normal mode macro to FALSE.

2) set the board to board macro TRUE.

3) load the program on Core0, but some problems happen.

Port didn't initialized, I checked the SPn_ERR_STAT and it,s value was " 0x00000001 ".

Q 1:

What should I do for solving this problem? I checked more STATUS registers but I couldn't solve the problem. Please guide.

I want the FPGA be master in the communication between DSP and FPGA, I found SP_GEN_CTL(0xB13C) that it's value was " 0x00000000 ".

Q 2:

Is it necessary to change the SP_GEN_CTL values?

Q 3:

When link between DSP and FPGA produce error(uninitialized), How can I debug it and solve the problem?

Regards