Hello everyone,
Issue:
I am trying to enable the GMII_1 interface to work with the 88E6131 GigE switch and having some trouble going through the documentation.
Background:
AM387x Technical Reference Manual
Section 9.3.4 pg 1478 - Explains the initialization and configuration of the CPSW.
Figure 9.2. pg 1427 - Shows 3PSW Subsystem Clocking Block Diagram
Figure 2-7 pg 412 - Shows Main PLL Structure
Section 9.3.4 pg 1478 - Explains the initialization and configuration of the CPSW.
Figure 2-10 pg 416 - Shows SERDES and ETHERNET Clock Structure
Questions:
It looks as if the SATA SERDES provides the reference clock to the GMII module of a 125MHz but I am unsure what registers to configure to properly set up the ethernet subsystem clocks?
On Figure 2-10 pg 415 it looks as if pcie_refp_clk affects the SATA SERDES do I need to write to the PCIE_PLLCFG register (Section 3.2.51), what registers do I need to access to enable the GMII_1 interface as I can't seem to determine this from the documentation?
Links to documentation:
AM387x Technical Reference Manual: http://www.ti.com/lit/ug/sprugz7b/sprugz7b.pdf
Regards,
-Brandon Reeves