6678 multicore programming problem

Hi,

I am using shared region method to achieve multicore programming. Currently I am doing a small test within two cores. I put a vector u in the MSMCSRAM, and use core 0 and core 1 to modify the first half and the second half data of the vector, respectively. I also put three variables flag, flag0 and flag1 in the MSMCSRAM to control synchronous issue. The initial values of flag, flag0 and flag1 are set to be NOP. Core 0 and core 1 begin to work when flag is set to START on core 0. After core 0 and core 1 have finished processing the data, flag0 and flag1 are set to FINISHED. Then at core 0, I examine the values of flag0 and flag1, if they are both FINISHED, I print the updated vector u.

My problem is, the value of flag1 is changed in core 1 and I have written the new value back to MSMCSRAM, however, when I examine it in core 0, it still remains to be the old value. My code is as below. Can anyone find what did I do wrong? Thanks very much! 

CORE 0:

#include <stdio.h>
#include <c6x.h>
#include "ti\csl\csl_cache.h"
#include "ti\csl\csl_cacheAux.h"

typedef enum{
 NOP,
 START,
 FINISHED
}FLAG;

#pragma DATA_SECTION(flag,".flags");
#pragma DATA_ALIGN(flag, CACHE_L1D_LINESIZE);
#pragma DATA_SECTION(flag0,".flags0");
#pragma DATA_ALIGN(flag0, CACHE_L1D_LINESIZE);
#pragma DATA_SECTION(flag1,".flags1");
#pragma DATA_ALIGN(flag1, CACHE_L1D_LINESIZE);
#pragma DATA_SECTION(u,".variables");
#pragma DATA_ALIGN(u, CACHE_L1D_LINESIZE);

volatile FLAG flag = NOP;
volatile FLAG flag0 = NOP;
volatile FLAG flag1 = NOP;
volatile float u[10]={1,2,3,4,5,6,7,8,9,10};

void main(void) {
 int i;
 CACHE_setL1PSize(CACHE_L1_32KCACHE);
 CACHE_setL1DSize(CACHE_L1_32KCACHE);
 CACHE_setL2Size(CACHE_0KCACHE);

 flag=START;
 CACHE_wbL1d((void*)&flag, CACHE_L1D_LINESIZE, CACHE_WAIT);
 CACHE_invL1d((void*)&u, CACHE_L1D_LINESIZE, CACHE_WAIT);
 for(i=0;i<5;i++)
 {
  u[i]=i*2+2.5+u[i];
 }
 CACHE_wbL1d((void*)&u, CACHE_L1D_LINESIZE, CACHE_WAIT);
 flag0=FINISHED;
 CACHE_wbL1d((void*)&flag0, CACHE_L1D_LINESIZE, CACHE_WAIT);
 while((flag0!=FINISHED) || (flag1!=FINISHED))
 {
  CACHE_invL1d((void*)&flag0, CACHE_L1D_LINESIZE, CACHE_WAIT);
  CACHE_invL1d((void*)&flag1, CACHE_L1D_LINESIZE, CACHE_WAIT);
 }
 CACHE_invL1d((void*)&u, CACHE_L1D_LINESIZE, CACHE_WAIT);
 for(i=0;i<10;i++)
 {
  printf("u[%d]=%f\n",i,u[i]);
 }
 flag=FINISHED;
 CACHE_wbL1d((void*)&flag, CACHE_L1D_LINESIZE, CACHE_WAIT);
}

CORE 1:

#include <stdio.h>
#include <c6x.h>
#include "ti\csl\csl_cache.h"
#include "ti\csl\csl_cacheAux.h"

typedef enum{
 NOP,
 START,
 FINISHED
}FLAG;

#pragma DATA_SECTION(flag,".flags");
#pragma DATA_ALIGN(flag, CACHE_L1D_LINESIZE);
#pragma DATA_SECTION(flag0,".flags0");
#pragma DATA_ALIGN(flag0, CACHE_L1D_LINESIZE);
#pragma DATA_SECTION(flag1,".flags1");
#pragma DATA_ALIGN(flag1, CACHE_L1D_LINESIZE);
#pragma DATA_SECTION(u,".variables");
#pragma DATA_ALIGN(u, CACHE_L1D_LINESIZE);

volatile FLAG flag = NOP;
volatile FLAG flag0 = NOP;
volatile FLAG flag1 = NOP;
volatile float u[10]={1,2,3,4,5,6,7,8,9,10};

void main(void) {
 int i;
 CACHE_setL1PSize(CACHE_L1_32KCACHE);
 CACHE_setL1DSize(CACHE_L1_32KCACHE);
 CACHE_setL2Size(CACHE_0KCACHE);

    while(flag != START)
  CACHE_invL1d((void*)&flag, CACHE_L1D_LINESIZE, CACHE_WAIT);
 CACHE_invL1d((void*)&u, CACHE_L1D_LINESIZE, CACHE_WAIT);
 for(i=5;i<10;i++)
 {
  u[i]=i*2+2.5+u[i];
 }
 CACHE_wbL1d((void*)&u, CACHE_L1D_LINESIZE, CACHE_WAIT);
 flag1=FINISHED;
 CACHE_wbL1d((void*)&flag1, CACHE_L1D_LINESIZE, CACHE_WAIT);
}

The Linker file of both core 0 and core 1:

-stack 0x0400
-heap  0x2000

MEMORY
{
  L2SRAM      : o = 0x00800000, l = 0x00080000
  MSMCSRAM       : o = 0x0c000000, l = 0x00400000
}

SECTIONS
{
  .cinit  : > L2SRAM
  .cio   : > L2SRAM
  .const  : > L2SRAM
  .data         : > L2SRAM
  .far   : > L2SRAM
  .fardata  : > L2SRAM
  .stack  : > L2SRAM
  .sysmem  : > L2SRAM
  .text         : > L2SRAM
  .neardata  : > L2SRAM
  .bss   : > L2SRAM

  .flags  : > MSMCSRAM
  .flags0  : > MSMCSRAM
  .flags1  : > MSMCSRAM
  .variables    : > MSMCSRAM
}