I really need to help about CC1101 communication:
In GFSK mode,the CC1101 can communicate sucessfully at FIFO mode,and I only adjust it to OOK mode,and nothing could be read from RX FIFO.And the following is register setting ,please help to check:
halSpiWriteReg(CCxxx0_IOCFG2,0x0d);
halSpiWriteReg(CCxxx0_IOCFG1,0x2e);
halSpiWriteReg(CCxxx0_IOCFG0,0x08);
// halSpiWriteReg(CCxxx0_FIFOTHR,0x0F);
// halSpiWriteReg(CCxxx0_FIFOTHR,0x07); //DN022 RX filter bandwidth > 325 kHz
halSpiWriteReg(CCxxx0_FIFOTHR,0x47); //DN022 RX filter bandwidth ≤ 325 kHz
halSpiWriteReg(CCxxx0_SYNC1,0xD3);
halSpiWriteReg(CCxxx0_SYNC0,0x91);
halSpiWriteReg(CCxxx0_PKTLEN,0x20);
halSpiWriteReg(CCxxx0_ADDR,0x00);
halSpiWriteReg(CCxxx0_CHANNR,0x00);
halSpiWriteReg(CCxxx0_PKTCTRL0,0x32);
halSpiWriteReg(CCxxx0_FSCTRL1,0x06);
halSpiWriteReg(CCxxx0_FSCTRL0,0x00);
halSpiWriteReg(CCxxx0_FREQ2,0x10); //433.92MHz
halSpiWriteReg(CCxxx0_FREQ1,0xB0);
halSpiWriteReg(CCxxx0_FREQ0,0x71);
halSpiWriteReg(CCxxx0_MDMCFG4,0xbB);
halSpiWriteReg(CCxxx0_MDMCFG3,0x83); //76K RX filter bandwidth = 203 kHz
// halSpiWriteReg(CCxxx0_MDMCFG4,0x26);
// halSpiWriteReg(CCxxx0_MDMCFG3,0x46);
// halSpiWriteReg(CCxxx0_MDMCFG2,0x35);
halSpiWriteReg(CCxxx0_MDMCFG2,0x30);
halSpiWriteReg(CCxxx0_MDMCFG1,0x42);
halSpiWriteReg(CCxxx0_MDMCFG0,0xf8);
halSpiWriteReg(CCxxx0_DEVIATN,0x15);
halSpiWriteReg(CCxxx0_MCSM2,0x07);
halSpiWriteReg(CCxxx0_MCSM1,0x30);
halSpiWriteReg(CCxxx0_MCSM0,0x18);
halSpiWriteReg(CCxxx0_FOCCFG,0x14);
halSpiWriteReg(CCxxx0_BSCFG,0x6C);
halSpiWriteReg(CCxxx0_AGCCTRL2, 0xff);
halSpiWriteReg(CCxxx0_AGCCTRL1, 0x00); //add mike
halSpiWriteReg(CCxxx0_AGCCTRL0, 0x91);
halSpiWriteReg(CCxxx0_WOREVT1, 0x43);
halSpiWriteReg(CCxxx0_WOREVT0, 0xB5); //add mike
halSpiWriteReg(CCxxx0_WORCTRL,0x68);
// halSpiWriteReg(CCxxx0_FREND1,0x56);
halSpiWriteReg(CCxxx0_FREND1,0xB6); //DN022 RX filter bandwidth > 101 kHz
// halSpiWriteReg(CCxxx0_FREND1,0x56); //DN022 RX filter bandwidth ≤ 101 kHz
halSpiWriteReg(CCxxx0_FREND0,0x11);
halSpiWriteReg(CCxxx0_FSCAL3,0xE9);
halSpiWriteReg(CCxxx0_FSCAL2,0x2A);
halSpiWriteReg(CCxxx0_FSCAL1,0x00);
halSpiWriteReg(CCxxx0_FSCAL0,0x1F);
// halSpiWriteReg(CCxxx0_TEST2,0x81);
// halSpiWriteReg(CCxxx0_TEST2,0x88); //DN022 RX filter bandwidth > 325 kHz
halSpiWriteReg(CCxxx0_TEST2,0x81); //DN022 RX filter bandwidth ≤ 325 kHz
// halSpiWriteReg(CCxxx0_TEST1,0x35);
// halSpiWriteReg(CCxxx0_TEST1,0x31); //DN022 RX filter bandwidth > 325 kHz
halSpiWriteReg(CCxxx0_TEST1,0x35); //DN022 RX filter bandwidth ≤ 325 kHz
halSpiWriteReg(CCxxx0_TEST0,0x09);
halSpiWriteReg(CCxxx0_RCCTRL1,0x41);
halSpiWriteReg(CCxxx0_RCCTRL0,0x00);
halSpiWriteReg(CCxxx0_FSTEST,0x59);
halSpiWriteReg(CCxxx0_PTEST,0x7F);