Hi,
On my target board BCLK is used as input to PLL.
Trying to use ADC Processing Blocks to filter some DC noise.
PLL initialization code:
I2Cwrite(CODEC_ADDR,0x00,0x00); //Initialize to Page 0
I2Cwrite(CODEC_ADDR,0x04,0x07); //PLL_CLKIN = BCLK
I2Cwrite(CODEC_ADDR,0x05,0x91); //CODEC_CLKIN = PLL_CLK , R=1, P=1
I2Cwrite(CODEC_ADDR,0x06,0x20); // J=32
I2Cwrite(CODEC_ADDR,0x12,0x81); // NADC = 1
I2Cwrite(CODEC_ADDR,0x13,0x84); // MADC = 4
I2Cwrite(CODEC_ADDR,0x14,0x80); // AOSR = 128
I2Cwrite(CODEC_ADDR,0x24,0x44);
I2Cwrite(CODEC_ADDR,0x3D,0x09); // PRB_R9
Above settings works ok , although for 44.1Khz ( bclk = 1411.2 Khz) it results ADC_FC = 88.2Khz .
I have verified bclk input to codec is 1411.2 Khz.
If I changed for example NADC = 2 ( So ADC_FC = 44.1Khz), gain/volume is reduced almost completely.
Also, according to app note, PRB_R9 can be used only with AOSR = 64.
If I change to PRB_R1/2 or any of PRB1 - PRB_R6 , it is not working correctly (noisy, gain reduced) .
Can you explain above 2 issues ( Double ADC_FS and mismatch ADC processing block) ?
Thanks,
Amit