ADS4229 input clock to output clock delay variation

I have a situation where I am using multiple ADS4229 ADCs to connect to different FPGAs and need the sampled data to arrive at each FPGA on the same clock edge, and assume the FPGAs are all phase locked.  The datasheet shows that tPDI, the clock propogation delay can vary by as much as 2.5ns which is quite a lot. I assume this is over a temperature variation, but I am not sure if this also include device-to-device variations as well. I would expect that two different ADS4229s at the same temperature would have a tPDI difference of picoseconds, not nanoseconds, but I could be wrong - this is not in the datasheet. Does anyone know what the maximum  device-to-device variation of tPDI and tSU could be if both devices are at roughly the same temperature?