Hi TI,
For admins >>> I'm sorry, opened the same post under the Stellaris forum accidentally
My CPU: AM3505, board is my final product board, not EVM3517.
Problem: having an issue with RX of McSPI1 reading 0's on two of my boards and 1's on another board that I have.
First, I am using mcSPI1 to connect to RTC and read from an ADC.
This is an example of SPI1 configuration for the RTC{
.modalias = "rtc-pcf2123", // RTC NXP2123
.bus_num = 1,
.chip_select = 1,
.max_speed_hz = 1000000,
.mode = SPI_CS_HIGH,
.controller_data = &tornado_mcspi_config,
},
OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
Important! It seems that this pin in HW is Ok. I have defined the SPI RX pin as a GPIO and tried to toggle the input with external signal, reading 0 or 1 according to the level I am setting. So, the GPIO works!
On my two first boards, I've tried to debug the omap2_mcspi.c device driver. The SPI write works fine. The problem is with the receive part only. I see the read occurs (for my 16bit reads) in the following portion of code:
if (rx != NULL) {
if (mcspi_wait_for_reg_bit(chstat_reg,
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
dev_err(&spi->dev, "RXS timed out\n");
goto out;
}
if (c == 2 && tx == NULL &&
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
omap2_mcspi_set_enable(spi, 0);
*rx++ = __raw_readl(rx_reg);
dev_vdbg(&spi->dev, "read-%d %04x\n",
word_len, *(rx - 1));
if (mcspi_wait_for_reg_bit(chstat_reg,
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
dev_err(&spi->dev,
"RXS timed out\n");
goto out;
}
c = 0;
} else if (c == 0 && tx == NULL) {
omap2_mcspi_set_enable(spi, 0);
}
*rx++ = __raw_readl(rx_reg);
dev_vdbg(&spi->dev, "read-%d %04x\n",
word_len, *(rx - 1));
Again, I've marked in RED the executing portion of code.if (rx != NULL) {
if (mcspi_wait_for_reg_bit(chstat_reg,
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
dev_err(&spi->dev, "RXS timed out\n");
goto out;
}
if (c == 2 && tx == NULL &&
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
omap2_mcspi_set_enable(spi, 0);
*rx++ = __raw_readl(rx_reg);
dev_vdbg(&spi->dev, "read-%d %04x\n",
word_len, *(rx - 1));
if (mcspi_wait_for_reg_bit(chstat_reg,
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
dev_err(&spi->dev,
"RXS timed out\n");
goto out;
}
c = 0;
} else if (c == 0 && tx == NULL) {
omap2_mcspi_set_enable(spi, 0);
}
*rx++ = __raw_readl(rx_reg);
dev_vdbg(&spi->dev, "read-%d %04x\n",
word_len, *(rx - 1));
Checked the config register, seems sensible, working in RX-transfer pio mode
Set CLK and MOSI pins as INPUT_PULLUP, as was recommended by TI's forum expert
Tried to change SPI speed and all modes including POL and PHA bits
Tried to increase the number of clocks between CS toggle and clock start (TCS from 0 to 3)
Tried to work with FIFO on the input (FFER)
Tried to loopback TX to RX using the IS bit to 1
Not sure about the clock divisor (WL) which is CLKD and now is 64.
Double checked the mux mode on this pin and it is correct
Checked the RX algorithm vs reference manual and it seems to be implemented in the code.
Tried to backport some similar problem changes to do with spi control
Tried to backport newer linux (3.9.something) but it was too far away.Studied also from the following posts:
[http://e2e.ti.com/support/arm/sitara_arm/f/416/t/86056.aspx]
[http://e2e.ti.com/support/arm/sitara_arm/f/416/p/86056/309155.aspx]
Please advise,
Regards
Yakir