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Mismatch in Fast Ethernet 4B5B encoding to CPRI CW mapping in AIF2

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How the AIF2 module arranges the bit order post 4b5b encoding  before it passes to CPRI layer 8b10b encoding to pack in CW.

  - As per my experiment, it seems, the AIF2 starts maping 5bits of upper nibble of Ethenet packet  in the top 5 bits in the CW byte0 and continue mapping bits. But as per the CPRI standard, it should start maping the 5bits of lower nibble of Ethernet packet  in the least 5bits in the CW byte0 and continue mapping.

What is  the configuration setting to start maping from lower nibble of Ethernet packet as per CPRI definition.

I tried setting Bitswap option but that converts the encoded data into Littel endian, but my requirement is it should continue to be in big endian.


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