fmcBus2Check function in spna106a.zip need not enable CPU ECC Detection and Correction Logic?

Hello Support,

In the spna106a.zip example for Cortex-R4 Initialization Code, there is a function called fmcBus2Check().

Can you please confirm whether I need to enable [SET] the following bits inside Cortex-R4 core :

C9_PMCR_Register_Content -- Bit 4  -- CPU Event Export -- Enable export of the events to the event bus for an external monitoring block

C1_Auxiliary_Control_Register -- Bit 25 -- ATCMPCEN -- ATCM parity or ECC check enable

C1_Auxiliary_Control_Register -- Bit 0 -- ATCMECEN -- ATCM external error enable

for fmcBus2Check() to PASS the test of SECDED within Flash Wrapper?

Do I need to SET all the above BITS or only a few of the above bits or NONE?

Or, is it a DON'T CARE for all the above bits for fmcBus2Check() to PASS the test?

Please let me know which of the above case is valid.

Thank you.

Regards

Pashan