* I issue this subject, because there were no answer from TI member for my question about PCM4204, 64 BCK problem.
* No answer means, there are no solution, and all agree about it.
Does the PCM4204 meets I2S specification?
I can say, No.
Philips Semiconductors I2S Bus specification(I2SBUS.pdf) described SD MSB starts 1 SCK clock after and ends one more SCK clock after WS changing.
That is Basic Interface Timming.
I can see many words "Philips I2S" in TI's "pcm4204.pdf", but the actual BCK clock has 64 pulse per L or R state for only 24bit I2S data.
64 pulses, not 32 pulses for only 24bit I2S!!! a TMS320C6743 has only 32 bit for one slot, no more, so the data transfer is doubtable.!
This is unfaithful description. I lost much time for development.
Do you agree with my opinion?
If somebody can reduce those 64 bck pulses to 32 bck pulses in master mode, please let me know.
(Table 7. of PCM4204.PDF, you can see 24-bit I2S, not 64bit)