Is there a separate TCM Hard Error Cache [64-Bit] for ATCM, B0TCM and B1TCM?

Hello Support,

Within TMS570LS Cortex-R4 core, is there a separate 64-Bit TCM Hard Error Cache for each of the TCM interface ports or a single 64 Bit TCM Hard Error Cache for all the 3 TCM Ports [ATCM, B0TCM and B1TCM]?

There are ATCM, B0TCM and B1TCM ports available.

Any Hard Error on either TCM ports are captured at the same Hard Error Cache [Single 64-Bit Buffer] or within different Hard Error Cache buffer for individual TCM Ports?

Thank you.
Regards
Pashan