Hello!
The Details:
CC430F6137, custom hardware (extremely low power 5-400uA), CCS, USB FET
Background:
I made a boo-boo in my hardware design and now realize now that I need to make the I/O on port 5.4 "interruptible" somehow. I know this isn't directly possible however I believe there are alternate solutions. I considered:
- (Dumb as nails) input polling inside main() loop
- Pro: Easy to code
- Con: burdens the CPU with wasteful code
- Using a comparator which triggers an ISR based on a ref of 1/2VCC.
- Pro: Would work with little software control
- Con: Wouldn't need this module except for this function & consumption is relatively high for this module (40-65uA or 20% of my budget)
- A timer with an ISR to pseudo-poll (instead of inside the main() loop)
- Pro: Simple, would work, low power, configurable latency (of registering IO state change)
- Con: the shorter the duration of the timer, less latency but higher CPU usage/current
Question(s):
Can I minimize software "up-time" to monitor this pin? Which of the above three options would you choose? Is there something more elegant you could suggest that I haven't considered?
Any thoughts would be great!
Thank you!
MK