RGMII direct connection to FPGA

Hi all,

We are trying to connect the AM3359 to FPGA using a standard RGMII bus, and Sitare-Linux 5.06.00.00 OS. There is no MDIO connection between the CPU and the FPGA. The FPGA is configured as Duplex-Full, Speed -1 Gig, Link-Up. The FPGA sets all RGMII electrical signals to be standard compliant (timing) with the CPU.

However, since no MDIO port exists, the CPU doesn't recognize this port (ETH1).

How can we force the CPU activate ETH1 to Link-up, Duplex-Full, Speed-1000, without getting that information from the FPGA?

Thanks,

Ran Kalif.