Part Number:ADC12J4000EVM
I do not have a question but I want to make a writeup of my work in the last weeks in order to help others achieve the same results much quicker.
Jim Seton from TI was kind enough to share some details on how to get big amounts of data from the ADC12J4000 using a Xilinx KCU105. Big thanks to the Xilinx developer who answered many of my questions.
The latest version of HSDC allows you to connect to a KCU105 via Ethernet. I documented the process here in detail: https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/567648
My listed steps are all correct, the only thing I had missed was setting the FMC VADJ to 1.8V using the "Enhanced COM Port" (see device manager, 115200 baud). The UART output is on the Standard COM Port (9600 baud).
The FPGA firmware that is bundled with HSDC Pro is apparently based on the file JESD204B_UltraScale_Hardware_Demo_2016_1_v1.3.zip from the Xilinx JESD Lounge which also includes the source code for the microblaze.
However the latest version on the JESD Lounge uhwd_2016_3_v1_0.zip can capture a lot more data (around 130 Million samples).
To get it to compile, you need to use the following steps:
1) Generate the bitstream in Vivado:
If you run the command:
set TARGET “TI”
Before running the command:
source ./script/built_it.tcl
The TI bitstreams will be generated.
Export the hardware to SDK
2) Compile the Microblaze Firmware in Xilinx SDK:
Open SDK
Add repository “\\uhwd_2016_3\sw_src\XilinxProcessorIPLib” using “Xilinx Tools->Repositories” from menu in SDK
Create “Xilinx project” called “uhwd” based on the lightweight IP echo server
Manually delete all the files in the created “uhwd\src” directory then paste in the files from uhwd_2016_3\sw_src\uhwd\src
Refresh the project in SDK
In order to capture more samples in HSDC you additionally need to set Max Samples = "536870912" in High Speed Data Converter Pro\KCU105 Details\Device and File Info.ini
Please note that even the uhwd_2016_3_v1_0.zip undersuses the RAM. The design only makes 1GB of the DDR4 available to the firmware. Additionally only 50% of the RAM is used for capture at the moment.
I am currently struggling with reworking the design to 2Gb usable RAM but it is great to have full control over the board.
Special thanks to Jim Seton and the nice people at Xilinx who have been wonderful in helping me to get this to work.