Quantcast
Channel: Forums - Recent Threads
Viewing all articles
Browse latest Browse all 262198

I2C not woking

$
0
0

hi all,

M new bie in I2C and m using MSP430F53xx series of controller for controlling and updating registers of PCM9211 using I2C, for this i picked up a example code of CCS 5.2 for sending multiple byte to slave but its not working and I'm unable to recognize whats wrong going here, so i tried I2C between two MSP430 and again its not working...

both hardware were individually working fine during I2C in my scope SCL or SDA is always High.

m attaching my code, please have a look

only modification in example code MSP430F530x_uscib0_i2c_08 is TxData sending

in my code P3.0 n P3.1 is configured as SDA,  SCL line, 10k external pullup is also used.

through this code i have to update various registers of PCM9211, so first byte of tx data is reg addr. and then reg. value and so on.

m pasting code here...

//******************************************************************************
// MSP430F530x Demo - USCI_B0 I2C Master TX multiple bytes to PCM9211 Slave
//
// Description: This demo connects MSP430's via the I2C bus. The master
// transmits to the slave. This is the MASTER CODE. It cntinuously
// transmits an array of data and demonstrates how to implement an I2C
// master transmitter sending multiple bytes using the USCI_B0 TX interrupt.
// ACLK = n/a, MCLK = SMCLK = BRCLK = default DCO = ~1.045MHz */

#include <msp430.h>

unsigned char *PTxData;                         // Pointer to TX data
unsigned char TXByteCtr;

const unsigned char TxData[ ] =             // Table of data to transmit,  reg loc. then value
{
0x40,0x33,
0x40,0xc0,
0x31,0x1A,
0x33,0x22,
0x20,0x00,
0x24,0x00,
0x26,0x81,
0x33,0x22,
0x42,0x02,
0X48,0X00,
0x49,0x00,
0x46,0xD7,
0x47,0xD7,
0x60,0x22,
0x61,0x10,
0x62,0x00,
0x78,0xDD,
0x6E,0x0F,
0x6F,0x40,
0x6B,0x22
};

int main(void)
{
unsigned int i;

WDTCTL = WDTPW | WDTHOLD;                                  // Stop WDT
P3SEL |= 0x03;                                                                   // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST;                                              // Enable SW reset
UCB0CTL0 = UCMST | UCMODE_3 | UCSYNC;        // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 | UCSWRST;                        // Use SMCLK, keep SW reset
UCB0BR0 = 12;                                                                 // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x80;                                                        // Slave Address is 048h
UCB0CTL1 &= ~UCSWRST;                                         // Clear SW reset, resume operation
UCB0IE |= UCTXIE;                                                          // Enable TX interrupt

while (1)
{
for(i=0;i<10;i++);                                                                // Delay required between transaction
PTxData = (unsigned char *)TxData;                              // TX array start address
                                                                                                  // transmit operation.
TXByteCtr = sizeof TxData;                                               // Load TX byte counter

UCB0CTL1 |= UCTR | UCTXSTT;                                   // I2C TX, start condition

__bis_SR_register(LPM0_bits | GIE);                            // Enter LPM0, enable interrupts
__no_operation();                                                               // Remain in LPM0 until all data
// is TX'd
while (UCB0CTL1 & UCTXSTP);                                      // Ensure stop condition got sent
}
}


#pragma vector = USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
{
switch(__even_in_range(UCB0IV,12))
{
case 0: break;                                                           // Vector 0: No interrupts
case 2: break;                                                            // Vector 2: ALIFG
case 4: break;                                                           // Vector 4: NACKIFG
case 6: break;                                                           // Vector 6: STTIFG
case 8: break;                                                          // Vector 8: STPIFG
case 10: break;                                                       // Vector 10: RXIFG
case 12:                                                                    // Vector 12: TXIFG 
if (TXByteCtr)                                                           // Check TX byte counter
{
UCB0TXBUF = *PTxData++;                                    // Load TX buffer
TXByteCtr--;                                                              // Decrement TX byte counter
}
else
{
UCB0CTL1 |= UCTXSTP;                                    // I2C stop condition
UCB0IFG &= ~UCTXIFG;                                     // Clear USCI_B0 TX int flag
__bic_SR_register_on_exit(LPM0_bits);            // Exit LPM0

default: break;
}
}

 

please assist as soon as possible whats wrong

I have few more queries 

1.how to check ACK n NACK signal using this code, because it may explains device is selected or i can check for successfully tx of last data then new data s transmitted 

2. or may i  blink an led during proper communication

please reply as soon as possible and looking for your valuable replies

regards:-

Sonu Verma 


Viewing all articles
Browse latest Browse all 262198

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>