Hi,
I'm designing a fast continuous ADC application. I've to acquire a signal array synchronized with two digital clock: one clock for array start (trigger) and the other for single sample (sample clock). So my source generate 256 signal (one every sample clock) starting at the "array start "clock.
I'm planning to solve the problem using:
Array start trigger -> Get 256 sample sync with sample clock -> generate interrupt -> in interrupt function copy and send data -> repeat
This should avoid the use of a double buffered acquisition because the interrupt time should be fast enough to manage the buffer content.
So I need a FIFO od 256 samples. Is this possibile?
At page 683 of the spnu499 manual is written: "The ADC module can support up to 1024 buffers. The device supports a maximum of 64 buffers for both the ADC modules.". What's the difference? Which one is the right maximum?
Can the ADC FIFO be sized to 256 (or slighlty more) samples?
If no: how to proceed to have a continuous ADC in group of 256 samples? There's something like a double buffered continuous acquisition?
In HalCoGen there are two settings for ADC memory size: one in "ADC Group" (FIFO size) and the other in "ADC Memory". The first seems to accept values hagher then 64 but the seconds seems limited to 64 bytes. Which is the difference?
Is there an example of single continous acquisition similar to the one I need?
Thank you,
Matteo