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Code security module(CSM) & ECSL in concerto families

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Hi every one, I want to secure my uploaded (programmed) code to the processor from reverse engineering and for this purpose there are code read protection in the other ARM based MCU from NXP ,ST ,etc which called CRP and no other extra option needed,while in the TI there are various security features and modules like CSM,ECSL ,OTP memories and derived execute only and jtag lock status which confused me completely. Is there any complete references manual about this security features ? I only want to limit my code to only run by processor and disable or debugging and code fetching states. with best regards.

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